公开(公告)号：FR2360992A1

公开(公告)日：1978-03-03

申请号：FR7720728

申请日：1977-06-30

Applicant: IBM

Inventor： JOHNSON WILLIAM S ,  KNEPPER RONALD W

IPC: H01L21/033 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8236 ,  H01L29/78

Abstract: A method for fabricating an N-channel silicon MOS field effect transistor on a P-type substrate. The structure retains the natural isolation between devices and the consequent higher device density in an integrated circuit structure than conventional double diffused MOS field effect transistor devices. The device is fabricated by using ion implantation to create an N-type surface layer in the channel and then overcompensating this layer to create a P-type region near the source by ion implanting P-type ions into the source junction region. The source to substrate capacitance is considerably less than that of conventional double diffused MOS devices which provides an improved circuit performance.

公开(公告)号：FR2285737A1

公开(公告)日：1976-04-16

申请号：FR7525143

申请日：1975-08-07

Applicant: IBM

Inventor： KNEPPER RONALD W ,  LANE RALPH D ,  LUDLOW PETER J ,  MOORE BARRY L

IPC: H03K17/08 ,  H02H3/08 ,  H02H3/093 ,  H02H7/20 ,  H03K17/082 ,  H03K19/0185

Abstract: An over current protect circuit for a common bus driver having a complementary pair FET output includes a pair of AND circuits responsive to the gate-source and drain-source voltages for charging separate time integrating capacitors. If a threshold charge is reached a latch is triggered, which in turn disables the driver via a NAND gate and Inverter, and discharges the active capacitor. The latch is reset by dropping the driver enable line. As an alternative, high driver current may be sensed by placing a resistor in series with each output FET and charging the associated capacitor in response to a high current through the resistor.

公开(公告)号：FR2379200A1

公开(公告)日：1978-08-25

申请号：FR7739914

申请日：1977-12-23

Applicant: IBM

Inventor： KNEPPER RONALD W

IPC: H03K19/017 ,  H03K19/0185 ,  H03K19/0944 ,  H03K17/60 ,  G11C7/00 ,  H03K19/08

公开(公告)号：DE2734694A1

公开(公告)日：1978-02-09

申请号：DE2734694

申请日：1977-08-02

Applicant: IBM

Inventor： JOHNSON WILLIAM S ,  KNEPPER RONALD W

IPC: H01L21/033 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8236 ,  H01L29/78

Abstract: A method for fabricating an N-channel silicon MOS field effect transistor on a P-type substrate. The structure retains the natural isolation between devices and the consequent higher device density in an integrated circuit structure than conventional double diffused MOS field effect transistor devices. The device is fabricated by using ion implantation to create an N-type surface layer in the channel and then overcompensating this layer to create a P-type region near the source by ion implanting P-type ions into the source junction region. The source to substrate capacitance is considerably less than that of conventional double diffused MOS devices which provides an improved circuit performance.

公开(公告)号：FR2372548A1

公开(公告)日：1978-06-23

申请号：FR7731535

申请日：1977-10-07

Applicant: IBM

Inventor： KNEPPER RONALD W

IPC: H03K19/0175 ,  H03K5/02 ,  H03K17/06 ,  H03K17/60 ,  H03K19/017 ,  H03K19/08 ,  H03K19/094 ,  H03K19/0944

Abstract: Disclosed is a field effect transistor (FET) driver circuit capable of full supply voltage signal swings and high switching speeds while dissipating relatively little power. The output is obtained from a node between two series connected enhancement mode devices. The first of these series connected enhancement mode devices receives an input signal at its gating electrode, while the second of this pair of series connected devices has its gating electrode capacitively coupled to the output node through a first gatable depletion mode device. The first depletion mode device is in a series electrical path with a second depletion mode device and an enhancement mode device. The second depletion mode device and the enhancement mode device in series therewith receive the same phase of the input signal as the gate of said one series connected output transistor while the first gated depletion mode device is either self-biased or gets a gating input that is out of phase therewith. A depletion mode device in parallel with one of the series connected enhancement mode output devices maintains the output node at a full supply voltage level.

公开(公告)号：CA1005925A

公开(公告)日：1977-02-22

申请号：CA173051

申请日：1973-06-04

Applicant: IBM

Inventor： ABBAS SHAKIR A ,  CHANG CHI S ,  FREEMAN LEO B JR ,  KNEPPER RONALD W

IPC: H01L27/10 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/535 ,  H01L27/108 ,  H01L29/06

公开(公告)号：DE2538453A1

公开(公告)日：1976-04-01

申请号：DE2538453

申请日：1975-08-29

Applicant: IBM

Inventor： KNEPPER RONALD W ,  LANE RALPH D ,  LUDLOW PETER J ,  MOORE BARRY L

IPC: H03K17/08 ,  H02H3/08 ,  H02H3/093 ,  H02H7/20 ,  H03K17/082 ,  H03K19/0185 ,  H02H7/12

Abstract: An over current protect circuit for a common bus driver having a complementary pair FET output includes a pair of AND circuits responsive to the gate-source and drain-source voltages for charging separate time integrating capacitors. If a threshold charge is reached a latch is triggered, which in turn disables the driver via a NAND gate and Inverter, and discharges the active capacitor. The latch is reset by dropping the driver enable line. As an alternative, high driver current may be sensed by placing a resistor in series with each output FET and charging the associated capacitor in response to a high current through the resistor.