公开(公告)号：EP1479103A4

公开(公告)日：2005-02-09

申请号：EP03731957

申请日：2003-01-16

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  CHU JACK O ,  FOGEL KEITH E ,  KOESTER STEPHEN J ,  SADANA DEVENDRA K ,  OTT JOHN ALBRECHT

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/225 ,  H01L21/324 ,  H01L21/337 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786 ,  H01L21/331

CPC classification number: H01L21/76243 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/2251 ,  H01L21/324 ,  H01L27/1203 ,  H01L29/66916 ,  Y10S438/938 ,  Y10T428/12674 ,  Y10T428/265 ,  Y10T428/31848

Abstract: A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate (10) material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer (14) which is present atop a barrier layer (12) that is resistant to the diffusion of Ge. Optionally forming a Si cap layer (18) over the SiGe or pure Ge layer (16), and thereafter heating the various layers at a temperature which permits interdiffusion of Ge throughtout the first single crystal Si layer (14), the optional Si cap (18) and the SiGe or pure Ge layer (16) thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer (12). Additional SiGe regrowth and/or formation of a strained epi-Si layer may follow the above steps. SiGe-on-insulator substrate materials as well as structures including at least the SiGe-on-insulator substrate material are also disclosed herein.

Abstract translation: 提供了一种形成薄的，高品质的弛豫SiGe绝缘体上的基板材料的方法，其首先包括形成第一单晶Si层的表面上的SiGe或纯Ge层，其存在的顶上即耐阻挡层 到Ge的扩散。 OPTIONALLY形成在SiGe或纯Ge层中的Si间隙层，并随后在其允许的Ge的相互扩散在整个第一单晶Si层的温度下加热的各种层，任选的Si盖和SiGe或纯Ge层，从而形成 基本松弛，单晶SiGe层在阻挡层上。 额外的SiGe再生长和/或形成的应变外延Si层的可遵循上述步骤。 上SiGe绝缘体基板材料以及包含结构至少在SiGe绝缘体上的基板材料，因此是在盘游离缺失。

公开(公告)号：EP1800345A4

公开(公告)日：2008-11-05

申请号：EP05725566

申请日：2005-03-15

Applicant: IBM

Inventor： CHU JACK O ,  COBB MICHAEL A ,  SAUNDERS PHILIP A ,  SHI LEATHEN

IPC: H01L21/762 ,  H01L21/18 ,  H01L29/12

CPC classification number: H01L21/76254 ,  H01L21/0245 ,  H01L21/0251 ,  H01L29/1054

Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25% atomic using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same

公开(公告)号：EP1570511A4

公开(公告)日：2009-06-10

申请号：EP03786848

申请日：2003-11-19

Applicant: IBM

Inventor： CHRISTIANSEN SILKE H ,  CHU JACK O ,  GRILL ALFRED ,  MOONEY PATRICIA M

IPC: H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/26506 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/7624 ,  H01L21/76251 ,  Y10S438/933

Abstract: A method to obtain thin (less than 300 nm) strain-relaxed Si1-xGex buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. less than 10 cm . The approach begins with the growth of a pseudomorphic or nearly pseudomorphic Si1-xGex layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operating with this method is dislocation nucleation at He-induced platelets (not bubbles) that lie below the Si/Si1-xGex interface, parallel to the Si(001) surface.

公开(公告)号：JPH11284220A

公开(公告)日：1999-10-15

申请号：JP5222499

申请日：1999-03-01

Applicant: IBM

Inventor： CHU JACK O ,  ISMAIL KHALID EZZELDIN ,  KOESTER STEVEN JOHN ,  KLEPSER BERND-ULRICH H

IPC: H01L31/10 ,  H01L27/144 ,  H01L31/0312 ,  H01L31/0352

Abstract: PROBLEM TO BE SOLVED: To simply integrate a high-speed and high-response photo detector in a monolithic form, by the method wherein a quantum well layer functions as a conductive channel so that a spacer layer separates a dopant in a supply layer from the conductive channel. SOLUTION: It comprises a single crystal semiconductor substrate 1, Si1-x Gex buffer layer 2 graded from x=0 to y ranging from 0.1 to 1.0, relaxing Si1-x Gex layer 3 of 0.25-10 μm thick, quantum well layer 4, undoped Si1-y Gey spacer layer 5 and doped Si1-y Gey supply layer 6. The relaxing Si1-x Gex layer 3 functions as an absorption region of a photo detector, the quantum well layer 4 can function as a conductive channel of a field effect transistor and the spacer layer 5 functions so as to separate a dopant in the supply layer from the conductive channel. Thus it is possible to manufacture a photo detector having an elevated speed and response, compared with a bulk Si.

公开(公告)号：JP2012186507A

公开(公告)日：2012-09-27

申请号：JP2012138161

申请日：2012-06-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHU JACK O ,  DELLINGER GABRIEL K ,  GRILL ALFRED ,  STEVEN J KOESTER ,  QIGING OUYANG ,  JEREMY D SCHAUB

IPC: H01L31/10 ,  H01L27/146 ,  H01L31/101

CPC classification number: H01L31/101

Abstract: PROBLEM TO BE SOLVED: To address a problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology.SOLUTION: The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing the Ge absorbing layer, low voltage operation by utilizing a thin absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of the group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

Abstract translation: 要解决的问题：解决与Si CMOS技术兼容的高速，高效率光电探测器的问题。 解决方案：该结构由薄SOI衬底上的Ge吸收层组成，并且利用隔离区，交替的n型和p型接触以及低电阻表面电极。 该器件利用掩埋绝缘层，通过利用Ge吸收层，通过利用薄吸收层和窄电极间距的低电压操作以及兼容性来兼容宽泛的光谱，利用掩埋绝缘层隔离下层衬底中产生的载流子，获得高量子效率 其CMOS器件凭借其平面结构和IV族吸收材料的使用。 用于制造光电检测器的方法使用在薄SOI或外延氧化物上的Ge的直接生长，以及随后的热退火以实现高质量的吸收层。 该方法限制可用于相互扩散的Si的量，从而允许Ge层退火，而不会导致Ge层被下面的Si大量稀释。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2003109918A

公开(公告)日：2003-04-11

申请号：JP2001300046

申请日：2001-09-28

Applicant: IBM

Inventor： CANAPERI DONALD F ,  COHEN GUY ,  RYAN HAN ,  OTT JOHN A ,  LOFARO MICHAEL ,  CHU JACK O

IPC: B24B37/00 ,  C08J5/14 ,  C09K3/14 ,  H01L21/304

Abstract: PROBLEM TO BE SOLVED: To provide a method and device by which a semiconductor substrate, a CMP tool, a brush cleaning tool, and a chemical wafer cleaning tool can be incorporated. SOLUTION: CMP is performed with a descending force of 1 psi, backward air pressure of 0.5 psi, platen speed of 50 rpm, carrier speed of 30 rpm, and slurry flow rate of 140 milliliter.

公开(公告)号：JP2007165867A

公开(公告)日：2007-06-28

申请号：JP2006311849

申请日：2006-11-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHU JACK O

IPC: H01L29/161 ,  H01L29/812 ,  H01L21/20 ,  H01L21/205 ,  H01L21/338 ,  H01L21/8232 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L27/095 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7782

Abstract: PROBLEM TO BE SOLVED: To provide a HEMT device and a CMOS device that are excellent in mobility and transconductance owing to a high-performance Ge channel structure. SOLUTION: A high-mobility Ge channel field effect transistor with a layered heterostructure incorporates multiple semiconductor layers on a semiconductor substrate, and a channel structure of a compressively strained epitaxial Ge layer having a higher barrier or a deeper confining quantum well and having an extremely high hole mobility for complementary MODFETs and MOSFETs. The present invention allows the mobility and transconductance of the field effect transistor to be improved to exceed those of a deep submicron state-of-the-art Si pMOSFET in addition to having a broad operating temperature range from a temperature (425 K) above room temperature down to an extremely low temperature (0.4 K) for enabling high device performance to be achieved even at low temperatures. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供由于高性能Ge沟道结构而具有优异的迁移率和跨导性的HEMT器件和CMOS器件。 解决方案：具有分层异质结构的高迁移率Ge沟道场效应晶体管在半导体衬底上并入多个半导体层，以及具有较高势垒或更深限制量子阱的压缩应变外延Ge层的沟道结构，并具有 互补型MODFET和MOSFET的空穴迁移率极高。 本发明允许将场效应晶体管的迁移率和跨导改善到超过深亚微米先进的Si pMOSFET的迁移率和跨导，同时具有从室以上的温度（425K）的宽工作温度范围 温度降到极低的温度（0.4K），以使即使在低温也能实现高的器件性能。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006019725A

公开(公告)日：2006-01-19

申请号：JP2005182416

申请日：2005-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEVIN K CHAN ,  CHU JACK O ,  KERN LIM ,  SHI LEATHEN

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/336 ,  H01L21/762 ,  H01L29/786

CPC classification number: H01L29/78687 ,  H01L21/2007 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/78603

Abstract: PROBLEM TO BE SOLVED: To provide a formation method for a heterostructure that can separate the fact that high strain is preferred in a strain Si layer and a Ge content in a low layer.
SOLUTION: A first multilayered structure 10 of a strained Si layer 14 and tensile strain SiGe alloy layer 16 constitute on a relaxation SiGe alloy layer 12. Then, a second multilayered structure 18, including an insulating layer 20, is formed on a substrate 22 and jointed with the first multilayered structure 10. After the insulating layer 20 and the SiGe alloy layer 16 are jointed, the relaxing SiGe alloy layer 12 is completely removed.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种异质结构的形成方法，其可以分离应变Si层中的高应变和低层中的Ge含量的事实。 解决方案：应变Si层14和拉伸应变SiGe合金层16的第一多层结构10构成弛豫SiGe合金层12.然后，在第一多层结构18上形成包括绝缘层20的第二多层结构18 基板22并与第一多层结构10连接。在绝缘层20和SiGe合金层16接合之后，完全去除弛豫SiGe合金层12。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005123580A

公开(公告)日：2005-05-12

申请号：JP2004234182

申请日：2004-08-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHU JACK O ,  KOESTER STEVEN J ,  OUYANG QIQING C

IPC: H01L29/06 ,  H01L21/20 ,  H01L21/335 ,  H01L21/338 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786 ,  H01L29/812

CPC classification number: H01L29/66431 ,  H01L29/7782 ,  Y10S438/933 ,  Y10S438/938

Abstract: PROBLEM TO BE SOLVED: To provide a high-mobility semiconductor layer and a structure of a MODFET (modulation-doped field-effect transistor) which include a high-mobility conduction channel and simultaneously maintain a counter dope to reduce a harmful short channel effect. SOLUTION: A high-performance n-MODFET transistor device is formed by providing an insulating gate dielectric on an Si cap layer, a gate electrode disposed on the insulating gate dielectric, and n-type source and drain contact areas which are disposed in contact with one side of the gate electrode and stretch from a surface of a multilayer structure into a p-type doped portion of a relaxed Si 1-X Ge X layer. This MODFET design includes the high-mobility conduction channel. This method forms a counter doped portion by using a standard technique such as ion implantation and bringing a high-mobility channel close to the counter doped portion without reducing a mobility. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供包括高迁移率传导通道的MODFET（调制掺杂场效应晶体管）的高迁移率半导体层和结构，并且同时保持反向掺杂以减少有害短路 渠道效应。 解决方案：通过在Si覆盖层上提供绝缘栅极电介质，设置在绝缘栅极电介质上的栅极电极和设置在绝缘栅极电介质上的n型源极和漏极接触区域来形成高性能n-MODFET晶体管器件 与栅电极的一侧接触并且从多层结构的表面拉伸成松弛的Si 1-X SB Ge x SB层的p型掺杂部分。 该MODFET设计包括高迁移率传导通道。 该方法通过使用诸如离子注入的标准技术形成反掺杂部分，并使高迁移率通道靠近反掺杂部分而不降低迁移率。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2005067677A2

公开(公告)日：2005-07-28

申请号：PCT/US2005000072

申请日：2005-01-04

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  CHAN KEVIN K ,  CHIDAMBARRAO DURESETI ,  CHRISTIANSEN SILKE H ,  CHU JACK O ,  DOMENICUCCI ANTHONY G ,  LEE KAM-LEUNG ,  MOCUTA ANDA C ,  OTT JOHN A ,  OUYANG QIQING C

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.

Abstract translation: 应变Fin场效应晶体管（FinFET）（及其形成方法）包括具有侧壁的松弛的第一材料和形成在第一材料的侧壁上的应变的第二材料。 松弛的第一材料和应变的第二材料形成FinFET的鳍。