公开(公告)号：GB2512804A

公开(公告)日：2014-10-08

申请号：GB201414384

申请日：2013-01-23

Applicant: IBM

Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  LE HIEN MINH ,  STUECHELI JEFFREY A

IPC: G06F12/08 ,  G06F15/167

Abstract: A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cachememory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.

公开(公告)号：DE112013000889T5

公开(公告)日：2014-10-16

申请号：DE112013000889

申请日：2013-01-23

Applicant: IBM

Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  LE HIEN MINH ,  STUECHELI JEFFREY A

IPC: G06F15/167

Abstract: Ein Mehrfachprozessor-Datenverarbeitungssystem enthält eine Vielzahl von Cachespeichern, die einen Cachespeicher enthalten. Als Reaktion auf ein Erkennen einer speichermodifizierenden Operation durch den Cachespeicher, die eine selbe Zieladresse wie diejenige einer ersten durch den Cachespeicher verarbeiteten Operation des Lesetyps angibt, stellt der Cachespeicher eine Neuversuchsantwort für die speichermodifizierende Operation bereit. Als Reaktion auf den Abschluss der Operation des Lesetyps tritt der Cachespeicher in einen Schiedsrichtermodus ein. Während er sich im Schiedsrichtermodus befindet, erhöht der Cachespeicher vorübergehend dynamisch eine Priorität irgendeiner speichermodifizierenden Operation, die auf die Zieladresse abzielt, im Verhältnis zu irgendeiner zweiten Operation des Lesetyps, die auf die Zieladresse abzielt.

公开(公告)号：GB2500964B

公开(公告)日：2014-06-11

申请号：GB201300936

申请日：2013-01-18

Applicant: IBM

Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  LE HIEN MINH ,  SHEN HUGH ,  STUECHELI JEFFREY A

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0842

公开(公告)号：GB2512804B

公开(公告)日：2015-03-04

申请号：GB201414384

申请日：2013-01-23

Applicant: IBM

Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  LE HIEN MINH ,  STUECHELI JEFFREY A

IPC: G06F12/08 ,  G06F15/167

Abstract: A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.

公开(公告)号：GB2500964A

公开(公告)日：2013-10-09

申请号：GB201300936

申请日：2013-01-18

Applicant: IBM

Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  LE HIEN MINH ,  SHEN HUGH ,  STUECHELI JEFFREY A

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0842

Abstract: Disclosed is a cache coherency protocol for multiprocessor data processing systems 104. The systems have a set of cache memories 230. A cache memory issues a read-type operation for a target cache line. While waiting for receipt of the target cache line, the cache memory monitors to detect a competing store-type operation for the target cache line. In response to receiving the target cache line, the cache memory installs the target cache line in the cache memory, and sets a coherency state of the target cache line installed in the cache memory based on whether the competing store-type operation is detected. The coherence state may be a first state indicating that the target cache line can source copies of the target cache line to requestors. In response to issuing the read-type operation, the cache memory receiving a coherence message indicating the state, wherein setting the coherence state for the target cache line comprises the cache memory setting the coherence state to the first state indicated by the coherence message if the competing store-type operation is not detected.