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    METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS
    2.
    发明公开
    METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS 审中-公开
    金属布线结构以集成到基片中的孔

    公开(公告)号：EP2313921A4

    公开(公告)日：2014-08-27

    申请号：EP09805365

    申请日：2009-07-28

    Applicant: IBM

    Inventor： COLLINS DAVID S ,  JOSEPH ALVIN ,  LINDGREN PETER J ,  STAMPER ANTHONY K ,  WATSON KIMBALL M

    IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H01L23/522 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.

    THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER
    3.
    发明公开
    THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER 有权
    ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER

    公开(公告)号：EP2250669A4

    公开(公告)日：2012-07-25

    申请号：EP09710899

    申请日：2009-02-11

    Applicant: IBM

    Inventor： LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K ,  STEIN KENNETH J

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

    Abstract translation: 贯通基板通孔包括在通孔基板孔周边的环形导体层和由环形导体层包围的塞子层。 一种用于制造穿通基底通孔的方法，包括在基底内形成盲孔，并且在盲孔内依次形成并随后在盲孔内进行平坦化，该保形导体层不填充填充孔的孔和塞层。 然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。

    THROUGH SILICON VIA LITHOGRAPHIC ALIGNMENT AND REGISTRATION
    4.
    发明申请
    THROUGH SILICON VIA LITHOGRAPHIC ALIGNMENT AND REGISTRATION 审中-公开
    通过光刻对齐和注册来实现硅通孔

    公开(公告)号：WO2011090852A2

    公开(公告)日：2011-07-28

    申请号：PCT/US2011020913

    申请日：2011-01-12

    Applicant: IBM ,  HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    Inventor： HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    IPC: H01L21/768

    CPC classification number: H01L21/76898 ,  G03F9/7076 ,  G03F9/708 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate (100; Figure 1) and lines the first opening with a protective liner. (102) The method deposits a material into the first opening (104) and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. (108) The method removes the material from the first opening through the second opening in the protective material. (110) The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

    Abstract translation: 制造集成电路结构的方法在衬底（100;图1）中形成第一开口并用保护性衬垫排列第一开口。 （102）该方法将材料沉积到第一开口（104）中并且在衬底上形成保护材料。 保护材料包括过程控制标记并且包括在第一开口上方并与第一开口对齐的第二开口。 （108）该方法通过保护材料中的第二开口从第一开口移除材料。 （110）过程控制标记包括保护材料内的凹部，其仅部分地延伸穿过保护材料，使得过程控制标记下方的部分基板不受移除材料的过程的影响。

    REMOVAL OF ETCHING PROCESS RESIDUAL IN SEMICONDUCTOR FABRICATION
    6.
    发明申请
    REMOVAL OF ETCHING PROCESS RESIDUAL IN SEMICONDUCTOR FABRICATION 审中-公开
    在半导体制造中去除蚀刻工艺残留

    公开(公告)号：WO2008091923A3

    公开(公告)日：2009-12-30

    申请号：PCT/US2008051758

    申请日：2008-01-23

    Applicant: IBM ,  HERRIN RUSSELL T ,  LINDGREN PETER J ,  STAMPER ANTHONY K

    Inventor： HERRIN RUSSELL T ,  LINDGREN PETER J ,  STAMPER ANTHONY K

    IPC: C11D7/00

    CPC classification number: H01L23/5223 ,  H01L21/02063 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure and methods for forming the same. A semiconductor fabrication method includes steps of providing a structure. A structure incl udes (a) a dielectric layer, (b) a first electrically conductive region buried in the dielectric layer, wherein the first electrically conductive region comprises a first electrically conductive material, and (c) a second electrically conductive region buried in the dielectric layer, wherein the second electrically conductive region comprises a second electrically conductive material being different from the first electrically conductive material. The method further includes the steps of creating a first hole and a second hole in the dielectric layer resulting in the first and second electrically conductive regions being exposed to a surrounding ambient through the first and second holes, respectively. Then, the method further includes the steps of introducing a basic solvent to bottom walls and side walls of the first and second holes.

    Abstract translation: 半导体结构及其形成方法。 半导体制造方法包括提供结构的步骤。 一种结构包括（a）介电层，（b）掩埋在所述电介质层中的第一导电区域，其中所述第一导电区域包括第一导电材料，和（c）第二导电区域， 介电层，其中第二导电区域包括不同于第一导电材料的第二导电材料。 该方法还包括以下步骤：在电介质层中形成第一孔和第二孔，导致第一和第二导电区域分别通过第一孔和第二孔暴露于周围环境。 然后，该方法还包括将碱性溶剂引入第一孔和第二孔的底壁和侧壁的步骤。

    Durchgehende Silizium Verbindung mit lithographischer Ausrichtung und Registrierung
    8.
    发明专利
    Durchgehende Silizium Verbindung mit lithographischer Ausrichtung und Registrierung 未知

    公开(公告)号：DE112011100134T5

    公开(公告)日：2012-10-04

    申请号：DE112011100134

    申请日：2011-01-12

    Applicant: IBM

    Inventor： SPROGIS EDMUND J ,  HERRIN RUSSELL T ,  LINDGREN PETER J ,  STAMPER ANTHONY K

    IPC: H01L21/768

    Abstract: Ein Verfahren zur Herstellung einer integrierten Schaltkreisstruktur bildet eine erste Öffnung in einem Substrat (100; 1) und liniert die erste Öffnung mit einer Schutzschicht. (102) Das Verfahren lagert Material in die erste Öffnung (104) ab und bildet ein Schutzmaterial über dem Substrat. Das Schutzmaterial enthält eine Prozess Kontrollmarkierung sowie eine zweite Öffnung oberhalb und ausgerichtet an der ersten Öffnung. (108) Das Verfahren entfernt das Material aus der ersten Öffnung durch die zweite Öffnung in dem Schutzmaterial. (110) Die Prozess-Kontrollmarkierung besteht aus einer Aussparung innerhalb des Schutzmaterials, die sich nur teilweise erstreckt durch das Schutzmaterial, so daß Teile des Substrats unter der Prozess Kontrollmarkierung nicht betroffen sind von dem Prozess des Entfernens des Materials.

    Through silicon via lithographic alignment and registration
    9.
    发明专利
    Through silicon via lithographic alignment and registration 未知

    公开(公告)号：GB2489859A

    公开(公告)日：2012-10-10

    申请号：GB201212589

    申请日：2011-01-12

    Applicant: IBM

    Inventor： HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    IPC: H01L21/768

    Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate (100; Figure 1) and lines the first opening with a protective liner. (102) The method deposits a material into the first opening (104) and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. (108) The method removes the material from the first opening through the second opening in the protective material. (110) The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

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