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    THROUGH SILICON VIA LITHOGRAPHIC ALIGNMENT AND REGISTRATION
    1.
    发明申请
    THROUGH SILICON VIA LITHOGRAPHIC ALIGNMENT AND REGISTRATION 审中-公开
    通过光刻对齐和注册来实现硅通孔

    公开(公告)号：WO2011090852A2

    公开(公告)日：2011-07-28

    申请号：PCT/US2011020913

    申请日：2011-01-12

    Applicant: IBM ,  HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    Inventor： HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    IPC: H01L21/768

    CPC classification number: H01L21/76898 ,  G03F9/7076 ,  G03F9/708 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate (100; Figure 1) and lines the first opening with a protective liner. (102) The method deposits a material into the first opening (104) and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. (108) The method removes the material from the first opening through the second opening in the protective material. (110) The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

    Abstract translation: 制造集成电路结构的方法在衬底（100;图1）中形成第一开口并用保护性衬垫排列第一开口。 （102）该方法将材料沉积到第一开口（104）中并且在衬底上形成保护材料。 保护材料包括过程控制标记并且包括在第一开口上方并与第一开口对齐的第二开口。 （108）该方法通过保护材料中的第二开口从第一开口移除材料。 （110）过程控制标记包括保护材料内的凹部，其仅部分地延伸穿过保护材料，使得过程控制标记下方的部分基板不受移除材料的过程的影响。

    REMOVAL OF ETCHING PROCESS RESIDUAL IN SEMICONDUCTOR FABRICATION
    4.
    发明申请
    REMOVAL OF ETCHING PROCESS RESIDUAL IN SEMICONDUCTOR FABRICATION 审中-公开
    在半导体制造中去除蚀刻工艺残留

    公开(公告)号：WO2008091923A3

    公开(公告)日：2009-12-30

    申请号：PCT/US2008051758

    申请日：2008-01-23

    Applicant: IBM ,  HERRIN RUSSELL T ,  LINDGREN PETER J ,  STAMPER ANTHONY K

    Inventor： HERRIN RUSSELL T ,  LINDGREN PETER J ,  STAMPER ANTHONY K

    IPC: C11D7/00

    CPC classification number: H01L23/5223 ,  H01L21/02063 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure and methods for forming the same. A semiconductor fabrication method includes steps of providing a structure. A structure incl udes (a) a dielectric layer, (b) a first electrically conductive region buried in the dielectric layer, wherein the first electrically conductive region comprises a first electrically conductive material, and (c) a second electrically conductive region buried in the dielectric layer, wherein the second electrically conductive region comprises a second electrically conductive material being different from the first electrically conductive material. The method further includes the steps of creating a first hole and a second hole in the dielectric layer resulting in the first and second electrically conductive regions being exposed to a surrounding ambient through the first and second holes, respectively. Then, the method further includes the steps of introducing a basic solvent to bottom walls and side walls of the first and second holes.

    Abstract translation: 半导体结构及其形成方法。 半导体制造方法包括提供结构的步骤。 一种结构包括（a）介电层，（b）掩埋在所述电介质层中的第一导电区域，其中所述第一导电区域包括第一导电材料，和（c）第二导电区域， 介电层，其中第二导电区域包括不同于第一导电材料的第二导电材料。 该方法还包括以下步骤：在电介质层中形成第一孔和第二孔，导致第一和第二导电区域分别通过第一孔和第二孔暴露于周围环境。 然后，该方法还包括将碱性溶剂引入第一孔和第二孔的底壁和侧壁的步骤。

    Through silicon via lithographic alignment and registration
    5.
    发明专利
    Through silicon via lithographic alignment and registration 未知

    公开(公告)号：GB2489859A

    公开(公告)日：2012-10-10

    申请号：GB201212589

    申请日：2011-01-12

    Applicant: IBM

    Inventor： HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    IPC: H01L21/768

    Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate (100; Figure 1) and lines the first opening with a protective liner. (102) The method deposits a material into the first opening (104) and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. (108) The method removes the material from the first opening through the second opening in the protective material. (110) The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

    Planar cavity MEMS and related structures, methods of manufacture and design structures
    6.
    发明专利
    Planar cavity MEMS and related structures, methods of manufacture and design structures 未知

    公开(公告)号：GB2494359B

    公开(公告)日：2015-01-14

    申请号：GB201300085

    申请日：2011-06-08

    Applicant: IBM

    Inventor： HERRIN RUSSELL T ,  JAHNES CHRISTOPHER V ,  STAMPER ANTHONY K ,  WHITE ERIC J

    IPC: B81C1/00 ,  H01H57/00

    Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes patterning a wiring layer to form at least one fixed plate and forming a sacrificial material on the wiring layer. The method further includes forming an insulator layer of one or more films over the at least one fixed plate and exposed portions of an underlying substrate to prevent formation of a reaction product between the wiring layer and a sacrificial material. The method further includes forming at least one MEMS beam that is moveable over the at least one fixed plate. The method further includes venting or stripping of the sacrificial material to form at least a first cavity.

    BIPOLARE TRANSISTORSTRUKTUR UND VERFAHREN ZUR BILDUNG DER STRUKTUR
    7.
    发明专利
    BIPOLARE TRANSISTORSTRUKTUR UND VERFAHREN ZUR BILDUNG DER STRUKTUR 未知

    公开(公告)号：DE112011101373T5

    公开(公告)日：2013-03-14

    申请号：DE112011101373

    申请日：2011-05-17

    Applicant: IBM

    Inventor： JOSEPH ALVIN J ,  STRICKER ANDREAS D ,  HARAME DAVID L ,  CAMILIO-CASTILIO RENATA ,  DAHLSTROM MATTIAS E ,  GRAY PETER B ,  HERRIN RUSSELL T

    IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737

    Abstract: Ausführungsformen einer verbesserten Transistorstruktur (100) (z. B. einer Bipolartransistor(BT)-Struktur oder Heteroübergang-Bipolartransistor(HBT)-Struktur) und ein Verfahren zur Bildung der Transistorstruktur (100) werden offenbart. Die Ausführungsformen der Struktur können eine dielektrische Schicht (130), die zwischen einer intrinsischen Basisschicht (120) und einer erhabenen extrinsischen Basisschicht (140) angeordnet ist, um die Kollektor-Basis-Kapazität Ccb zu reduzieren, einen seitenwanddefinierten leitenden Streifen (150) für eine Verbindungszone von der intrinsischen Basisschicht (120) zur extrinsischen Basisschicht (140), um den Basis-Widerstand Rb zu reduzieren, und eine dielektrische Abstandsschicht (160) zwischen der extrinsischen Basisschicht (140) und einer Emitterschicht (180) aufweisen, um die Basis-Emitter-Kapazität Cbe zu reduzieren. Die Ausführungsformen des Verfahrens erlauben die Selbstjustierung des Emitters zu Basiszonen und erlauben zudem die selektive Anpassung der Geometrien verschiedener Merkmale (z. B. der Dicke der dielektrischen Schicht (130), der Breite des leitenden Streifens (150), der Breite der dielektrischen Abstandsschicht (160) und der Breite der Emitterschicht (180)), um die Transistorleistungsfähigkeit zu optimieren.

    Bipolar transistor structure and method of forming the structure
    8.
    发明专利
    Bipolar transistor structure and method of forming the structure 未知

    公开(公告)号：GB2494358A

    公开(公告)日：2013-03-06

    申请号：GB201300063

    申请日：2011-05-17

    Applicant: IBM

    Inventor： CAMILLO-CASTILLO RENATA ,  DAHLSTROM MATTIAS E ,  GRAY PETER B ,  HARAME DAVID L ,  HERRIN RUSSELL T ,  JOSEPH ALVIN ,  STRICKER ANDREAS D

    IPC: H01L29/06 ,  H01L21/331 ,  H01L29/10 ,  H01L29/66 ,  H01L29/732 ,  H01L29/737

    Abstract: Disclosed are embodiments of an improved transistor structure (100) (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure (100). The structure embodiments can incorporate a dielectric layer (130) sandwiched between an intrinsic base layer (120) and a raised extrinsic base layer (140) to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap (150) for an intrinsic base layer (120) to extrinsic base layer (140) link-up region to reduce base resistance Rb and a dielectric spacer (160) between the extrinsic base layer (140) and an emitter layer (180) to reduce base- emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer (130), the width of the conductive strap (150), the width of the dielectric spacer (160) and the width of the emitter layer (180)) to be selectively adjusted in order to optimize transistor performance.

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