公开(公告)号：EP1461828A4

公开(公告)日：2005-09-28

申请号：EP02803310

申请日：2002-11-07

Applicant: IBM

Inventor： VOLANT RICHARD P ,  BISSON JOHN C ,  COTE DONNA R ,  DALTON TIMOTHY J ,  GROVES ROBERT A ,  PETRARCA KEVIN S ,  STEIN KENNETH J ,  SUBBANNA SESHADRI

IPC: B81B3/00 ,  B81C1/00 ,  H01H49/00 ,  H01H59/00

CPC classification number: B81C1/00246 ,  B81B2201/016 ,  B81B2201/018 ,  B81B2203/0127 ,  B81B2207/07 ,  B81C1/00611 ,  B81C2201/0122 ,  B81C2203/0735 ,  H01G5/40 ,  H01H59/0009

Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

公开(公告)号：EP2286444A4

公开(公告)日：2012-11-21

申请号：EP09747138

申请日：2009-04-28

Applicant: IBM

Inventor： ESHUN EBENEZER E ,  HE ZHONG-XIANG ,  RASSEL ROBERT M ,  COOLBAUGH DOUGLAS ,  GEBRESELASIE EPHREM G ,  WANG PING-CHUAN ,  KIM DEOK-KEE ,  KOTHANDARAMAN CHANDRASEKHARAN ,  ROBSON NORMAN W ,  MOY DAN ,  SAFRAN JOHN M ,  STEIN KENNETH J ,  HO HERBERT L ,  YAN HONGWEN

IPC: H01L23/525 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：WO02058117A3

公开(公告)日：2003-08-28

申请号：PCT/EP0201049

申请日：2002-01-16

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP ,  IBM FRANCE

Inventor： ARMACOST MICHAEL D ,  AUGUSTIN ANDREAS K ,  FRIESE GERALD R ,  HEIDENREICH JOHN E III ,  HUECKEL GARY R ,  STEIN KENNETH J

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 mu ) with a bottom etch stop layer (104), a composite bottom plate (110) having an aluminium layer below a TiN layer, an oxide capacitor dielectric (120), and a top plate (130) of TiN. The process involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

Abstract translation: 在铜技术中的平行平板电容器形成在其下方没有铜（0.3μm以内）的区域，底部蚀刻停止层（104），在TiN层下方具有铝层的复合底板（110）， 氧化物电容器电介质（120）和TiN的顶板（130）。 该方法包括蚀刻顶板以留下电容器区域，将底板蚀刻到具有在所有侧面上的边缘的较大底部区域; 在电容器顶板的顶表面下沉积具有较高材料质量的层间电介质; 打开接触孔到顶板和底板，并且将互连件下降到两步工艺，其在穿过底板上方的氮化物盖层之后部分地打开下互连和顶板上的氮化物盖层，然后切穿电容器电介质 并完成氮化物盖层的穿透。

公开(公告)号：WO2004038916A3

公开(公告)日：2004-08-12

申请号：PCT/EP0312399

申请日：2003-09-18

Applicant: IBM ,  IBM FRANCE

Inventor： CHINTHAKINDI ANIL K ,  GROVES ROBERT A ,  STEIN KENNETH J ,  SUBBANNA SESHADRI ,  VOLANT RICHARD P

IPC: B81B7/00 ,  B81C1/00 ,  H01G5/011 ,  H01G5/18 ,  H03J3/18 ,  B81B3/00 ,  H01G5/16

CPC classification number: H01G5/18 ,  B81B2201/01 ,  H01G5/011 ,  Y10S257/924

Abstract: A three-dimensional micro-electromechanical (MEM) varactor is described wherein a movable beam (50) and fixed electrodes (51) are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the "chip side" while the fixed bottom electrode is fabricated on a separated substrate "carrier side". Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and "flipped over", aligned and joined to the "carrier" substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used. Upon fabrication, the MEMS device is completely encapsulated, requiring no additional packaging of the device. Further, since alignment and bonding can be done on a wafer scale (wafer scale MEMS packaging), an improved device yield can be obtained at a lower cost.

Abstract translation: 描述了三维微机电（MEM）变容二极管，其中可移动光束（50）和固定电极（51）分别制造在彼此耦合的分离的基板上。 具有梳状驱动电极的可移动光束在“芯片侧”上制造，而固定底部电极制造在分离的基板“载体侧”上。 在衬底的两个表面上制造器件时，芯片侧器件被切割并“翻转”，对准并接合到“载体”衬底以形成最终器件。 梳状驱动（鳍）电极用于致动，同时电极的运动提供电容的变化。 由于所涉及的驱动力恒定，可以获得大的电容调谐范围。 该装置的三维方面具有较大的表面积。 当提供大的纵横比特征时，可以使用较低的致动电压。 在制造时，MEMS器件被完全封装，不需要额外的器件封装。 此外，由于可以在晶片规模（晶片级MEMS封装）上进行取向和接合，所以可以以更低的成本获得改进的器件产量。

公开(公告)号：EP2250669A4

公开(公告)日：2012-07-25

申请号：EP09710899

申请日：2009-02-11

Applicant: IBM

Inventor： LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K ,  STEIN KENNETH J

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

Abstract translation: 贯通基板通孔包括在通孔基板孔周边的环形导体层和由环形导体层包围的塞子层。 一种用于制造穿通基底通孔的方法，包括在基底内形成盲孔，并且在盲孔内依次形成并随后在盲孔内进行平坦化，该保形导体层不填充填充孔的孔和塞层。 然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。

公开(公告)号：JP2002280458A

公开(公告)日：2002-09-27

申请号：JP2002002593

申请日：2002-01-09

Applicant: IBM

Inventor： VOLANT RICHARD P ,  JOHN M COTTE ,  PETRARCA KEVIN S ,  STEIN KENNETH J

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To provide a process for fabricating a metal/insulator/metal capacitor(MIM cap) structure in a semiconductor substrate efficiently at low cost. SOLUTION: A metal oxide layer 18 is formed on a deposited underlying metal layer 16 using an anode oxidation procedure, a second metal 20 is deposited thereon and planarized by chemical mechanical polishing or other procedure to fabricate a metal/insulator/metal capacitor structure in a semiconductor substrate. This process is not a conventional etching process for forming a capacitor structure but an extra process. This process is applicable to the field of damascene structure and can be used for forming a variety of capacitor structures while decreasing the number of mask layers required for formation.

公开(公告)号：JP2004319983A

公开(公告)日：2004-11-11

申请号：JP2004085745

申请日：2004-03-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN HUAJIE ,  SUBBANNA SESHADRI ,  JAGANNATHAN BASANTH ,  GREGORY G FREEMAN ,  AHLGREN DAVID C ,  ANGELL DAVID ,  SCHONENBERG KATHRYN T ,  STEIN KENNETH J ,  JAMIN FEN F

IPC: H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/737 ,  H01L29/78

CPC classification number: H01L21/8249 ,  H01L27/0623

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a BiCMOS integrated circuit having a raised external base.
SOLUTION: This method comprises a step for forming a polycrystal silicon layer on the surface of a gate dielectric substance 18 provided on a substrate having a device section 14 in which a bipolar transistor is formed and a device section 16 in which a CMOS transistor is formed. Then, the polycrystal silicon layer is patterned, and a sacrifice polycrystal silicon layer is formed above the device section in which the bipolar transistor is formed and the section around it. Meanwhile, a gate conductor is provided in the device section in which the CMOS transistor is formed at the same time. Then, a spacer 30 is provided around each of the gate conductor. Then a part of the sacrifice polycrystal silicon layer on the bipolar device section is selectively removed to provide an opening in the device section in which the bipolar transistor is formed. Then the bipolar transistor having a raised external base 58 is formed at the opening.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于形成具有凸起的外部基底的BiCMOS集成电路的方法。 解决方案：该方法包括在设置在其上形成有双极晶体管的器件部分14的衬底上的栅极电介质18的表面上形成多晶硅层的步骤，以及器件部分16，其中CMOS 形成晶体管。 然后，对多晶硅层进行构图，在形成双极型晶体管的器件部分上方形成牺牲多晶硅层，并在其周围形成截面。 同时，在同时形成CMOS晶体管的器件部分中提供栅极导体。 然后，围绕每个栅极导体设置间隔件30。 然后，选择性地去除双极器件部分上牺牲多晶硅层的一部分，以在其中形成双极晶体管的器件部分中提供开口。 然后在开口处形成具有升高的外部基座58的双极晶体管。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004214649A

公开(公告)日：2004-07-29

申请号：JP2003421677

申请日：2003-12-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHINTHAKINDI ANIL K ,  JENG SHWU-JEN ,  LOFARO MICHAEL F ,  SCHNABEL CHRISTOPHER M ,  STEIN KENNETH J

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L23/522 ,  H01L27/04 ,  H01L27/08

CPC classification number: H01L28/20 ,  H01L23/5223 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10S438/97 ,  Y10T29/49082 ,  Y10T29/49155 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a process which reduces the number of treatment processes, eliminates a problem about an integration of the process such as a via landing on a resistor and a capacitor, and improves a performance and a property to be used. SOLUTION: An insulating oxide layer is accumulated, a lower electrode of the capacitor is formed by accumulating a metal layer, and a dielectric of the capacitor is formed by accumulating a dielectric layer on the metal layer. the dielectric and the lower electrode of the capacitor are patterned by a lithography and etched. The upper electrode of the capacitor is formed on the capacitor dielectric by accumulating the metal layer, a thin-film resistor with different structure is formed at one side of the capacitor, and a nitride etching-stopping cap is accumulated on the upper electrode of the capacitor and on the metal layer of the thin-film resistor. The upper electrode of the capacitor and the thin-film resistor are patterned by lithography and etched. An interlayer dielectric layer ILD is accumulated on the upper electrode of the capacitor and on the thin-film resistor. An ILD wiring level is patterned by the lithography and etched. An integrated copper structure is formed by accumulating a liner layer and a copper layer. A final structure of MIMCAP is formed by chemical-mechanical polishing of the integrated copper structure. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：WO2009140052A3

公开(公告)日：2010-01-21

申请号：PCT/US2009041861

申请日：2009-04-28

Applicant: IBM ,  ESHUN EBENEZER E ,  HE ZHONG-XIANG ,  RASSEL ROBERT M ,  COOLBAUGH DOUGLAS ,  GEBRESELASIE EPHREM G ,  WANG PING-CHUAN ,  KIM DEOK-KEE ,  KOTHANDARAMAN CHANDRASEKHARAN ,  ROBSON NORMAN W ,  MOY DAN ,  SAFRAN JOHN M ,  STEIN KENNETH J ,  HO HERBERT L ,  YAN HONGWEN

Inventor： ESHUN EBENEZER E ,  HE ZHONG-XIANG ,  RASSEL ROBERT M ,  COOLBAUGH DOUGLAS ,  GEBRESELASIE EPHREM G ,  WANG PING-CHUAN ,  KIM DEOK-KEE ,  KOTHANDARAMAN CHANDRASEKHARAN ,  ROBSON NORMAN W ,  MOY DAN ,  SAFRAN JOHN M ,  STEIN KENNETH J ,  HO HERBERT L ,  YAN HONGWEN

IPC: H01L21/335

CPC classification number: H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

Abstract translation: 半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成 部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。 场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。 熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料 栅电极。

公开(公告)号：WO03001584A8

公开(公告)日：2004-05-27

申请号：PCT/US0219789

申请日：2002-06-19

Applicant: IBM

Inventor： JAGANNATHAN BASANTH ,  JENG SHWU-JEN ,  JOHNSON JEFFREY B ,  JOHNSON ROBB A ,  LANZEROTTI LOUIS D ,  STEIN KENNETH J ,  SUBBANNA SESHADRI

IPC: H01L21/331 ,  H01L21/8249 ,  H01L29/737 ,  H01L31/11

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/7378

Abstract: A method for making a non-self-aligned, heterojunction bipolar transistor includes forming extrinsic base regions (70) with a PFET source/drain implant aligned with the polysilicon in an emitter stack but which are not directly aligned with an emitter opening defined in that stack. This is achieved by making the emitter pedestal (66) wider than the emitter opening. This advantageously removes the dependency of alignment between the extrinsic base regions and the emitter opening, thereby resulting in fewer process steps, reduced thermal cycles, and improved speed.

Abstract translation: 一种用于制造非自对准的异质结双极晶体管的方法包括：在发射极堆叠中形成具有与多晶硅对准的PFET源极/漏极注入的非本征基极区域（70），但并不直接对准在该区域中限定的发射极开口 叠加。 这通过使发射器基座（66）比发射器开口更宽来实现。 这有利地消除了非本征基区和发射极开口之间的对准的依赖性，从而导致更少的工艺步骤，减少的热循环和改进的速度。