公开(公告)号：JP2004214649A

公开(公告)日：2004-07-29

申请号：JP2003421677

申请日：2003-12-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHINTHAKINDI ANIL K ,  JENG SHWU-JEN ,  LOFARO MICHAEL F ,  SCHNABEL CHRISTOPHER M ,  STEIN KENNETH J

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L23/522 ,  H01L27/04 ,  H01L27/08

CPC classification number: H01L28/20 ,  H01L23/5223 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10S438/97 ,  Y10T29/49082 ,  Y10T29/49155 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a process which reduces the number of treatment processes, eliminates a problem about an integration of the process such as a via landing on a resistor and a capacitor, and improves a performance and a property to be used. SOLUTION: An insulating oxide layer is accumulated, a lower electrode of the capacitor is formed by accumulating a metal layer, and a dielectric of the capacitor is formed by accumulating a dielectric layer on the metal layer. the dielectric and the lower electrode of the capacitor are patterned by a lithography and etched. The upper electrode of the capacitor is formed on the capacitor dielectric by accumulating the metal layer, a thin-film resistor with different structure is formed at one side of the capacitor, and a nitride etching-stopping cap is accumulated on the upper electrode of the capacitor and on the metal layer of the thin-film resistor. The upper electrode of the capacitor and the thin-film resistor are patterned by lithography and etched. An interlayer dielectric layer ILD is accumulated on the upper electrode of the capacitor and on the thin-film resistor. An ILD wiring level is patterned by the lithography and etched. An integrated copper structure is formed by accumulating a liner layer and a copper layer. A final structure of MIMCAP is formed by chemical-mechanical polishing of the integrated copper structure. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：WO2012047770A3

公开(公告)日：2012-06-21

申请号：PCT/US2011054521

申请日：2011-10-03

Applicant: IBM ,  CHANG JOSEPHINE B ,  CHARNS LESLIE ,  CUMMINGS JASON E ,  GUILLORN MICHAEL A ,  HUPKA LUKASZ J ,  KOLI DINESH ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB W ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

Inventor： CHANG JOSEPHINE B ,  CHARNS LESLIE ,  CUMMINGS JASON E ,  GUILLORN MICHAEL A ,  HUPKA LUKASZ J ,  KOLI DINESH ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB W ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

IPC: H01L21/304 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/31053 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

Abstract: A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.

Abstract translation: 平面化方法包括在第一化学机械抛光步骤中平坦化半导体晶片以去除覆盖层并平坦化顶层，从而在顶层之上留下厚度的顶层材料。 顶层材料在第二化学机械抛光步骤中被平坦化，以进一步去除顶层并暴露第二材料和第三材料的下层，使得顶层材料对第二材料对第三材料的选择性在 约1：1至约2：1：1，以提供平面形貌。

公开(公告)号：WO2012047780A3

公开(公告)日：2012-06-14

申请号：PCT/US2011054545

申请日：2011-10-03

Applicant: IBM ,  ANDO TAKASHI ,  CHARNS LESLIE ,  CUMMINGS JASON ,  HUPKA JUKASZ J ,  KOLI DINESH R ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

Inventor： ANDO TAKASHI ,  CHARNS LESLIE ,  CUMMINGS JASON ,  HUPKA JUKASZ J ,  KOLI DINESH R ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

IPC: H01L21/336 ,  H01L21/304 ,  H01L29/78

CPC classification number: H01L21/31053 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

Abstract: Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.

Abstract translation: 用于抛光多个电介质层以形成替换金属栅极结构的方法包括第一化学机械抛光步骤，以去除覆盖层并平坦化顶层以在栅极结构上留下平坦化的厚度。 第二化学机械抛光步骤包括去除厚度以暴露栅极结构的电介质的下面覆盖的表面，其中浆料被配置成基本上等同地抛光顶层和下面的被覆表面以实现平面形貌。 采用第三种化学机械抛光步骤来去除栅极结构的电介质并露出栅极导体。

公开(公告)号：GB2497253A

公开(公告)日：2013-06-05

申请号：GB201305907

申请日：2011-10-03

Applicant: IBM ,  JSR CORP

Inventor： ANDO TAKASHI ,  CHARNS LESLIE ,  CUMMINGS JASON E ,  HUPKA JUKASZ J ,  KOLI DINESH ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB W ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/66

Abstract: Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.

公开(公告)号：GB2497253B

公开(公告)日：2014-03-19

申请号：GB201305907

申请日：2011-10-03

Applicant: IBM ,  JSR CORP

Inventor： ANDO TAKASHI ,  CHARNS LESLIE ,  CUMMINGS JASON E ,  HUPKA JUKASZ J ,  KOLI DINESH ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB W ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/66

公开(公告)号：CA2288621A1

公开(公告)日：2000-06-04

申请号：CA2288621

申请日：1999-11-08

Applicant: IBM

Inventor： LOFARO MICHAEL F

IPC: B24B27/00 ,  B24B41/06 ,  H01L21/304 ,  H01L21/02

Abstract: A wafer polishing tool is disclosed which includes a polishing platen which is rotatable about a central platen axis, and a wafer carrier which supports a wafer for rotational movement to cause a portion of a surface of the wafer to only intermittently contact a polishing surface of the platen while the wafer rotates. The polishing tool may include a plurality of vertically stacked polishing platens which are rotatable about a central platen axis, and a plurality of stacked wafer carriers, wherein each carrier supports a wafer for rotational movement and vertical movement into contact with one of the polishing platens. During polishing, the carrier pack maintains the wafers in uninterrupted contact with the platen over less than entire surfaces of the wafers.

公开(公告)号：DE112011103351B4

公开(公告)日：2014-03-13

申请号：DE112011103351

申请日：2011-10-03

Applicant: IBM ,  JSR CORP

Inventor： ANDO TAKASHI ,  CHARNS LESLIE ,  CUMMINGS JASON ,  HUPKA JUKASZ J ,  KOLI DINESH R ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB W ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

IPC: H01L21/336 ,  B24B1/00 ,  H01L21/283 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/768 ,  H01L29/78

Abstract: Verfahren zum Polieren für ein Ausbilden von Strukturen mit metallischen Ersatz-Gates, aufweisend: einen ersten chemisch-mechanischen Polierschritt, um Materialüberschuss zu entfernen und eine oberste Schicht zu planarisieren, um eine planarisierte Dicke über einer Gate-Struktur zurückzulassen; einen zweiten chemisch-mechanischen Polierschritt, aufweisend ein Entfernen der planarisierten Dicke durch gleichmäßiges Polieren und dadurch Entfernen der obersten Schicht und Freilegen einer darunterliegenden bedeckten Oberfläche eines Dielektrikums der Gate-Struktur mit einem Poliermittel, sodass eine ebene Topografie erreicht wird; und ein dritter chemisch-mechanischer Polierschritt, um das Dielektrikum von der Gate-Struktur zu entfernen und einen Gate-Leiter freizulegen.

公开(公告)号：GB2497490B

公开(公告)日：2014-02-26

申请号：GB201305905

申请日：2011-10-03

Applicant: IBM ,  JSR CORP

Inventor： CHANG JOSEPHINE ,  CHARNS LESLIE ,  CUMMINGS JASON E ,  GUILLORN MICHAEL ,  HUPKA LUKASZ J ,  KOLI DINESH ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB W ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

IPC: H01L21/304 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/786

公开(公告)号：GB2497490A

公开(公告)日：2013-06-12

申请号：GB201305905

申请日：2011-10-03

Applicant: IBM ,  JSR CORP

Inventor： CHANG JOSEPHINE ,  CHARNS LESLIE ,  CUMMINGS JASON E ,  GUILLORN MICHAEL ,  HUPKA LUKASZ J ,  KOLI DINESH ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB W ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

IPC: H01L21/304 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/786

Abstract: A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.

公开(公告)号：DE102012216091B4

公开(公告)日：2016-10-20

申请号：DE102012216091

申请日：2012-09-11

Applicant: IBM

Inventor： LOFARO MICHAEL F

IPC: H01L21/673 ,  B23Q3/08 ,  B24B7/16 ,  B24B37/10 ,  B65G49/07 ,  H01L21/304

Abstract: Vorrichtung (100; 200; 300; 400), welche eine Trägerplattform (68) umfasst, wobei die Trägerplattform (68) Folgendes umfasst: eine Grundplatte (34) mit N Löchern darin, wobei N eine Ganzzahl größer als 2 ist; N Wellen (38), wobei jede einzelne der N Wellen (38) sich durch eines der N Löcher erstreckt, einen Endteil hat, welcher aus einer Oberfläche der Grundplatte (34) auf einer Seite der Grundplatte (34) hervorsteht, und an einer bewegungsübertragenden Baueinheit (32A, 32B, 32C; 32A, 32B, 32C, 32D, 32E) befestigt ist, welche so konfiguriert ist, dass sie die N Wellen (38) auf einer entgegengesetzten Seite der Grundplatte (34) um ihre jeweiligen Achsen dreht; und N Trägeradapter (39), wobei jeder einzelne der N Trägeradapter (39) an jedem einzelnen der N Endteile befestigt ist und so konfiguriert ist, dass er einen Substratträger (72) halten kann; und wobei die Vorrichtung (100; 200; 300; 400) ein Transportbahnsystem (64, 16; 64, 16; 350) umfasst, welches so konfiguriert ist, dass es in die Trägerplattform (68) eingreift und die Trägerplattform (68) in einer Richtung senkrecht zu den Achsen der N Wellen transportiert.