Abstract:
An apparatus and method attaching a heatsink to a surface of an electronic package comprising a substrate, an integrated circuit chip attached to the surface of the substrate, an encapsulant encapsulating the integrated circuit chip and contacting at least a portion of the surface of the substrate, and an orifice formed in the top portion of the encapsulant to attach the heatsink to the surface of the electronic package. The heatsink may be attached and removed as desired to allow for package identification or rework.
Abstract:
A PACKAGE FOR MOUNTING AN INTEGRATED CIRCUIT CHIP (30, 52) TO A CIRCUIT BOARD (48) OR THE LIKE IS PROVIDED. THE PACKAGE INCLUDES A CHIP CARRIER (10) WHICH HAS A METAL SUBSTRATE (12) INCLUDING FIRST AND SECOND OPPOSED FACES. A DIELECTRIC COATING (20) IS PROVIDED ON AT LEAST ONE OF THE FACES, WHICH PREFERABLY IS LESS THAN ABOUT 20 MICRONS IN THICKNESS, AND PREFERABLY HAS A DIELECTRIC CONSTANT FROM ABOUT 35 TO ABOUT 4.0. ELECTRICAL CIRCUITRY IS DISPOSED ON THE DIELECTRIC COATING, SAID CIRCUITRY INCLUDING CHIP MOUNTING PADS (22), CONNECTION PADS (24) AND CIRCUIT TRACES (26) CONNECTING THE CHIP MOUNTING PADS TO THE CONNECTION PADS. AN IC CHIP IS MOUNTED BY FLIP CHIP OR WIRE BONDING OR ADHESIVE CONNECTION ON THE FACE OF THE METAL SUBSTRATE WHICH HAS THE DIELECTRIC COATING THEREON. IN ANY CASE, THE IC CHIP IS ELECTRICALLY CONNECTED TO THE CHIP MOUNTING PADS EITHER BY THE SOLDER BALL (54) OR WIRE BOND (36) CONNECTIONS. ELECTRICAL LEADS (38, 60) EXTEND FROM THE CONNECTION PADS ON THE CHIP CARRIER AND ARE CONNECTED TO CORRESPONDING PADS ON A CIRCUIT BOARD OR THE LIKE TO PROVIDE I/O SIGNALS FOR THE IC CHIP. IN CERTAIN EMBODIMENTS, ADDITIONAL HEAT SINKS (62) CAN BE ATTACHED TO THE CHIP CARRIER AND, ALSO IN CERTAIN EMBODIMENTS, CHIPS CAN BE MOUNTED ON BOTH SIDES OF THE CHIP CARRIER TO INCREASE THE CAPACITY OF THE CHIP CARRIER. (FIG. 1)
Abstract:
A PACKAGE FOR MOUNTING AN INTEGRATED CIRCUIT CHIP (30, 52) TO A CIRCUIT BOARD (48) OR THE LIKE IS PROVIDED. THE PACKAGE INCLUDES A CHIP CARRIER (10) WHICH HAS A METAL SUBSTRATE (12) INCLUDING FIRST AND SECOND OPPOSED FACES. A DIELECTRIC COATING (20) IS PROVIDED ON AT LEAST ONE OF THE FACES, WHICH PREFERABLY IS LESS THAN ABOUT 20 MICRONS IN THICKNESS, AND PREFERABLY HAS A DIELECTRIC CONSTANT FROM ABOUT 35 TO ABOUT 4.0. ELECTRICAL CIRCUITRY IS DISPOSED ON THE DIELECTRIC COATING, SAID CIRCUITRY INCLUDING CHIP MOUNTING PADS (22), CONNECTION PADS (24) AND CIRCUIT TRACES (26) CONNECTING THE CHIP MOUNTING PADS TO THE CONNECTION PADS. AN IC CHIP IS MOUNTED BY FLIP CHIP OR WIRE BONDING OR ADHESIVE CONNECTION ON THE FACE OF THE METAL SUBSTRATE WHICH HAS THE DIELECTRIC COATING THEREON. IN ANY CASE, THE IC CHIP IS ELECTRICALLY CONNECTED TO THE CHIP MOUNTING PADS EITHER BY THE SOLDER BALL (54) OR WIRE BOND (36) CONNECTIONS. ELECTRICAL LEADS (38, 60) EXTEND FROM THE CONNECTION PADS ON THE CHIP CARRIER AND ARE CONNECTED TO CORRESPONDING PADS ON A CIRCUIT BOARD OR THE LIKE TO PROVIDE I/O SIGNALS FOR THE IC CHIP. IN CERTAIN EMBODIMENTS, ADDITIONAL HEAT SINKS (62) CAN BE ATTACHED TO THE CHIP CARRIER AND, ALSO IN CERTAIN EMBODIMENTS, CHIPS CAN BE MOUNTED ON BOTH SIDES OF THE CHIP CARRIER TO INCREASE THE CAPACITY OF THE CHIP CARRIER. (FIG. 1)
Abstract:
A PACKAGE FOR MOUNTING AN INTEGRATED CIRCUIT CHIP (30, 52) TO A CIRCUIT BOARD (48) OR THE LIKE IS PROVIDED. THE PACKAGE INCLUDES A CHIP CARRIER (10) WHICH HAS A METAL SUBSTRATE (12) INCLUDING FIRST AND SECOND OPPOSED FACES. A DIELECTRIC COATING (20) IS PROVIDED ON AT LEAST ONE OF THE FACES, WHICH PREFERABLY IS LESS THAN ABOUT 20 MICRONS IN THICKNESS, AND PREFERABLY HAS A DIELECTRIC CONSTANT FROM ABOUT 35 TO ABOUT 4.0. ELECTRICAL CIRCUITRY IS DISPOSED ON THE DIELECTRIC COATING, SAID CIRCUITRY INCLUDING CHIP MOUNTING PADS (22), CONNECTION PADS (24) AND CIRCUIT TRACES (26) CONNECTING THE CHIP MOUNTING PADS TO THE CONNECTION PADS. AN IC CHIP IS MOUNTED BY FLIP CHIP OR WIRE BONDING OR ADHESIVE CONNECTION ON THE FACE OF THE METAL SUBSTRATE WHICH HAS THE DIELECTRIC COATING THEREON. IN ANY CASE, THE IC CHIP IS ELECTRICALLY CONNECTED TO THE CHIP MOUNTING PADS EITHER BY THE SOLDER BALL (54) OR WIRE BOND (36) CONNECTIONS. ELECTRICAL LEADS (38, 60) EXTEND FROM THE CONNECTION PADS ON THE CHIP CARRIER AND ARE CONNECTED TO CORRESPONDING PADS ON A CIRCUIT BOARD OR THE LIKE TO PROVIDE I/O SIGNALS FOR THE IC CHIP. IN CERTAIN EMBODIMENTS, ADDITIONAL HEAT SINKS (62) CAN BE ATTACHED TO THE CHIP CARRIER AND, ALSO IN CERTAIN EMBODIMENTS, CHIPS CAN BE MOUNTED ON BOTH SIDES OF THE CHIP CARRIER TO INCREASE THE CAPACITY OF THE CHIP CARRIER. (FIG. 1)
Abstract:
A PACKAGE FOR MOUNTING AN INTEGRATED CIRCUIT CHIP (30, 52) TO A CIRCUIT BOARD (48) OR THE LIKE IS PROVIDED. THE PACKAGE INCLUDES A CHIP CARRIER (10) WHICH HAS A METAL SUBSTRATE (12) INCLUDING FIRST AND SECOND OPPOSED FACES. A DIELECTRIC COATING (20) IS PROVIDED ON AT LEAST ONE OF THE FACES, WHICH PREFERABLY IS LESS THAN ABOUT 20 MICRONS IN THICKNESS, AND PREFERABLY HAS A DIELECTRIC CONSTANT FROM ABOUT 35 TO ABOUT 4.0. ELECTRICAL CIRCUITRY IS DISPOSED ON THE DIELECTRIC COATING, SAID CIRCUITRY INCLUDING CHIP MOUNTING PADS (22), CONNECTION PADS (24) AND CIRCUIT TRACES (26) CONNECTING THE CHIP MOUNTING PADS TO THE CONNECTION PADS. AN IC CHIP IS MOUNTED BY FLIP CHIP OR WIRE BONDING OR ADHESIVE CONNECTION ON THE FACE OF THE METAL SUBSTRATE WHICH HAS THE DIELECTRIC COATING THEREON. IN ANY CASE, THE IC CHIP IS ELECTRICALLY CONNECTED TO THE CHIP MOUNTING PADS EITHER BY THE SOLDER BALL (54) OR WIRE BOND (36) CONNECTIONS. ELECTRICAL LEADS (38, 60) EXTEND FROM THE CONNECTION PADS ON THE CHIP CARRIER AND ARE CONNECTED TO CORRESPONDING PADS ON A CIRCUIT BOARD OR THE LIKE TO PROVIDE I/O SIGNALS FOR THE IC CHIP. IN CERTAIN EMBODIMENTS, ADDITIONAL HEAT SINKS (62) CAN BE ATTACHED TO THE CHIP CARRIER AND, ALSO IN CERTAIN EMBODIMENTS, CHIPS CAN BE MOUNTED ON BOTH SIDES OF THE CHIP CARRIER TO INCREASE THE CAPACITY OF THE CHIP CARRIER. (FIG. 1)
Abstract:
AN APPARATUS AND METHOD ATTACHING A HEATSINK (214) TO A SURFACE OF AN ELECTRONIC PACKAGE (200, 300, 300, 500, 600) COMPRISING A SUBSTRATE (202), AN INTEGRATED CIRCUIT CHIP (204) ATTACHED TO THE SURFACE OF THE SUBSTRATE, AN ENCAPSULANT (206, 226, 306, 326, 406, 506, 606) ENCAPSULATING THE INTEGRATED CIRCUIT CHIP AND CONTACTING AT LEAST A PORTION OF THE SURFACE OF THE SUBSTRATE, AND AN ORIFICE (208, 308) FORMED IN THE TOP PORTION OF THE ENCAPSULANT TO ATTACH THE HEATSINK TO THE SURFACE OF THE ELECTRONIC PACKAGE. THE HEATSINK MAY BE ATTACHED AND REMOVED AS DESIRED TO ALLOW FOR PACKAGE IDENTIFICATION OR REWORK.
Abstract:
In an integrated circuit package employing solder bump technology, a metal layer placed on the surface of a substrate below an array of bonding pads is split and displaced from its axis at selected locations to preserve electrical continuity, but to also lower the height of an insulating solder mask layer at those locations.
Abstract:
A PACKAGE FOR MOUNTING AN INTEGRATED CIRCUIT CHIP (30, 52) TO A CIRCUIT BOARD (48) OR THE LIKE IS PROVIDED. THE PACKAGE INCLUDES A CHIP CARRIER (10) WHICH HAS A METAL SUBSTRATE (12) INCLUDING FIRST AND SECOND OPPOSED FACES. A DIELECTRIC COATING (20) IS PROVIDED ON AT LEAST ONE OF THE FACES, WHICH PREFERABLY IS LESS THAN ABOUT 20 MICRONS IN THICKNESS, AND PREFERABLY HAS A DIELECTRIC CONSTANT FROM ABOUT 35 TO ABOUT 4.0. ELECTRICAL CIRCUITRY IS DISPOSED ON THE DIELECTRIC COATING, SAID CIRCUITRY INCLUDING CHIP MOUNTING PADS (22), CONNECTION PADS (24) AND CIRCUIT TRACES (26) CONNECTING THE CHIP MOUNTING PADS TO THE CONNECTION PADS. AN IC CHIP IS MOUNTED BY FLIP CHIP OR WIRE BONDING OR ADHESIVE CONNECTION ON THE FACE OF THE METAL SUBSTRATE WHICH HAS THE DIELECTRIC COATING THEREON. IN ANY CASE, THE IC CHIP IS ELECTRICALLY CONNECTED TO THE CHIP MOUNTING PADS EITHER BY THE SOLDER BALL (54) OR WIRE BOND (36) CONNECTIONS. ELECTRICAL LEADS (38, 60) EXTEND FROM THE CONNECTION PADS ON THE CHIP CARRIER AND ARE CONNECTED TO CORRESPONDING PADS ON A CIRCUIT BOARD OR THE LIKE TO PROVIDE I/O SIGNALS FOR THE IC CHIP. IN CERTAIN EMBODIMENTS, ADDITIONAL HEAT SINKS (62) CAN BE ATTACHED TO THE CHIP CARRIER AND, ALSO IN CERTAIN EMBODIMENTS, CHIPS CAN BE MOUNTED ON BOTH SIDES OF THE CHIP CARRIER TO INCREASE THE CAPACITY OF THE CHIP CARRIER. (FIG. 1)