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公开(公告)号：US3781793A
公开(公告)日：1973-12-25
申请号：US3781793D
申请日：1972-04-10
Applicant: IBM
CPC classification number: G06F11/10
Abstract: An error detection system of n inputs is adaptable for fabrication in large scale integrated circuit form. An integrated circuit logic array provides a parity check in response to digital signals received via X and Y decoders. Reduction in the number of array cells and the X and Y driving decoder circuits is obtained by interconnecting even parity subgroups and odd parity subgroups of lines from the X and Y decoders to provide even master parity lines and odd master parity lines. A logic array having less than 2n operative cells compares the signals on the master lines and generates an error parity signal.
Abstract translation: n个输入的误差检测系统适用于大规模集成电路形式的制造。 集成电路逻辑阵列响应于经由X和Y解码器接收的数字信号提供奇偶校验。 通过将来自X和Y解码器的偶校验子组和奇校验子组相互连接来提供阵列单元数量和X和Y驱动解码器电路的减少，以提供偶校验奇偶校验线和奇数主奇偶校验线。 具有小于2n个操作单元的逻辑阵列比较主线上的信号并产生误差奇偶校验信号。
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2.发明授权
公开(公告)号：US3731375A
公开(公告)日：1973-05-08
申请号：US3731375D
申请日：1970-04-16
Applicant: IBM
Inventor： AGUSTA B , BARDELL P , CASTRUCCI P , HENLE R , PECORATO R
IPC: G11C11/411 , H03K3/286 , H03K3/288 , B01J17/00 , H01L1/16
CPC classification number: H03K3/286 , G11C11/4113 , H03K3/288 , Y10S438/917
Abstract: A method of making a monolithic integrated semiconductor structure that has a plurality of functionally isolated individual cells that are electrically interconnected. Each of the cells is an object of mirror image cell that is vertically, horizontally and diagonally displaced from the object cell. The plurality of cells provide a memory array with electrical components of each memory cell composed of active and passive semiconductor devices. Other importance aspects of the structure include underpass connections and active devices in a common portion of the structure which are electrically interconnected at the same node potential by means of a highly doped buried region within the common portion of the structure.
Abstract translation: 一种制造单片集成半导体结构的方法，其具有电互连的多个功能隔离的单个电池。 每个单元是从对象单元垂直，水平和对角地移位的镜像单元的对象。 多个单元提供具有由有源和无源半导体器件组成的每个存储单元的电气部件的存储器阵列。 该结构的其他重要方面包括在结构的公共部分中的地下通道连接和有源器件，其通过在结构的公共部分内的高掺杂掩埋区在相同的节点电位电互连。
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3.发明授权
公开(公告)号：US3823348A
公开(公告)日：1974-07-09
申请号：US3311970
申请日：1970-04-16
Applicant: IBM
Inventor： CASTRUCCI P , HENLE R , AGUSTA B , BARDELL P , PECORARO R
IPC: G11C11/411 , H03K3/286 , H03K3/288 , H01L5/00
CPC classification number: H03K3/286 , G11C11/4113 , H03K3/288
Abstract: A monolithic integrated semiconductor structure is described that has a plurality of functionally isolated individual cells that are electrically interconnected. Each of the cells is an object or mirror image cell that is vertically, horizontally and diagonally displaced from the object cell. The plurality of cells provide a memory array with electrical components of each memory cell composed of active and passive semiconductor devices. Other important aspects of the structure include underpass connections and active devices in a common portion of the structure which are electrically interconnected at the same node potential by means of a highly doped buried region within the common portion of the structure. In particular, a sophisticated packaging scheme for containing such a highly complex array of memory cells is disclosed.
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公开(公告)号：US3798606A
公开(公告)日：1974-03-19
申请号：US3798606D
申请日：1971-12-17
Applicant: IBM
IPC: G06F12/16 , G06F1/00 , G06F7/00 , G06F11/10 , G06F11/18 , G06F15/78 , H03H9/02 , G06F11/00 , G06F13/00
CPC classification number: G06F11/184 , G06F1/00 , G06F7/00 , G06F11/10
Abstract: A monolithic circuit bit partitioned computer system for processing M bits of data comprising a substrate for providing electrical interconnection paths to a plurality of M monolithic circuit modules. Each of the M modules includes distinct decoder means, memory means, elemental quasi-arithmetic means and control circuitry, and each of the M modules are uniquely associated with the distinct ones of the M bits of data for collectively and universally processing the M bits of data.
Abstract translation: 一种用于处理M位数据的单片电路位分割计算机系统，包括用于提供到多个M个单片电路模块的电互连路径的衬底。 每个M个模块包括不同的解码器装置，存储装置，元素准运算装置和控制电路，并且M个模块中的每一个与M个数据位中的不同的一个数据唯一地相关联，用于共同和普遍地处理M位 数据。
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Patent Agency Ranking
公开(公告)号：SE306762B
公开(公告)日：1968-12-09
申请号：SE136061
申请日：1961-02-09
Applicant: IBM
Inventor： DOMENICO R , HENLE R
Abstract: 894,248. Electric selective signalling systems. INTERNATIONAL BUSINESS MACHINES CORPORATION. Feb. 9, 1961 [Feb. 10, 1960], No. 4816/61. Class 40 (1). [Also in Group XL (b)] A system for automatically detecting, indicating and replacing a faulty component in logical circuits and for changing the logical function performed by the circuits includes a plurality of amplifiers 1-4, Fig. 5a, which are normally maintained in one signal translating condition, and a plurality of switching elements such as photo-contacts, which couple individual outputs of amplifiers 1-4 to individual inputs of the amplifiers, and are responsive to selectable patterns of applied control effects, e.g. illumination, to modify the signal translating condition of selected ones of amplifiers 1-4. Each amplifier 1-4 may form part of a NOR circuit, as shown in Fig. 2b, in which the transistor is normally biased to a non-conducting condition, but the negative bias is reduced and the transistor rendered conducting if one of the photocontacts # is illuminated. The NOR circuits may be interconnected to perform any logical function as desired by selectively illuminating the photo-contacts, for example by means of a pattern of holes or transparent areas in a card. film or tape. In Fig. 5a, amplifiers 1, 2, 3 are connected in a closed loop to form an oscillator whose output is taken from amplifier 3 on line 46 which is connected to line 49 through an illuminated photo-contact. If one of amplifiers 1, 2, 3 becomes faulty there is no input to amplifier 55, relay 57 operates to close contacts 58 and a pulse is transmitted to a pattern-shifting mechanism 43 which then advances card 29 in the direction shown by arrow 66 so that a fresh pattern of holes is selected, the function performed by amplifiers 1-4 being the same but with the faulty component replaced by another. For example, if amplifier 1 was faulty, amplifiers 2, 3, 4 may be connected in a closed loop, the output being taken from amplifier 4 on lines 45, 49. The system not only provides automatic replacement of faulty components, but may also indicate which component is faulty, e.g. by displaying a number on the side of the card showing which amplifier is not connected in the circuit. It is stated that the system may be used as a substitute for a plugboard in a computer, for example for controlling the arithmetic unit functions.
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公开(公告)号：SE366864B
公开(公告)日：1974-05-06
申请号：SE1253370
申请日：1970-09-15
Applicant: IBM
IPC: F22B21/06 , G11C17/06 , G11C17/14 , G11C17/16 , H01L23/525 , H01L27/00 , H01L27/102 , G11C17/00
Abstract: A read only memory having the capability of being written into once after manufacture. The cells of the memory are capable of being fused or permanently altered by directing a fusing current to the selected cells. The cell is a monolithic semiconductor device comprising a diode to be biased in a forward direction and a diode to be biased in the reverse direction structured so as to form back-to-back diodes. The reverse diode has a lower reverse breakdown voltage than the forward diode, and a metal connection, unconnected to any remaining circuit elements contacts the semiconductor device between diode junctions. The fusing current causes a metal-semiconductor alloy to form and short out the reverse diode.
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公开(公告)号：CA925170A
公开(公告)日：1973-04-24
申请号：CA42787
申请日：1969-02-13
Applicant: IBM
Inventor： HENLE R
IPC: G11C11/402 , G11C11/411 , G11C11/414 , H03K3/012 , H03K3/356
Abstract: 1,207,084. Bi-stable circuits. INTERNATIONAL BUSINESS MACHINES CORP. 30 Jan., 1969 [6 March, 1968], No. 5522/69. Heading H3T. Each time a bi-stable T1-T2 is switched on by a pulsed power supply V c it reassumes that state it had before switching off, by virtue of internally stored charge whose rate of discharge is made low in relation to the pulsing frequency by arranging semi-conductor switching means such as diodes D1, D2 to confine the discharge to a relatively high impedance path. For example, if T 1 is on, and T2 off when the supply V c goes off, the diodes D1, D2 become non- conductive, transistor T2 can be disregarded since it was off, and transistor T1 can be regarded as a series combination of base-collector diode and capacitance (12, 13, Fig. 2, not shown) and emitter-base diode and capacitance (14, 15). The relatively high voltage which was at T2 collector 4 before switch-off can only discharge through the e-b diode (14) from the capacitance (15). The impedance of the diode (14) rises non-linearly and by a substantial amount when the voltage (at 4) has fallen to about 0À8 volts, and this order of voltage is therefore available when the power switches on again to ensure correct resetting of the bi-stable. The collector voltages in the embodiment swing between 0À05V and 0À75 volts approximately. An emitter coupled pair of transistors (T3, T4, Fig. 3, not shown) having a current source transistor (T5) perform read and write functions, the control pulse applied (at 20) to the current source transistor being preferably coincident with a power supply turn-on pulse. An OR-gate (Fig. 4, not shown) ensures that the power turn-on pulses V c are produced when either normal timing pulses are received (at 44) during normal regeneration, or a control pulse is received (at 46) from a logic decode matrix. T1 and T2 may be multiemitter transistors.
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公开(公告)号：SE345930B
公开(公告)日：1972-06-12
申请号：SE454767
申请日：1967-03-31
Applicant: IBM
Inventor： AGUSTA B , HENLE R , PECORARO R , BARDELL P , CASTRUCCI P
IPC: H01L27/08 , G11C11/411 , H03K3/286 , H03K3/288 , H01L19/00
Abstract: A monolithic integrated memory arrangement comprising, in combination, a plurality of individual memory cells, functionally isolated and electrically interconnected, in which each of said memory cells is object or corresponding to another memory cell mirroring mirror image, in vertical, horizontal and diagonal direction. (Machine-translation by Google Translate, not legally binding)
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