-
1.
-
公开(公告)号:CA1148273A
公开(公告)日:1983-06-14
申请号:CA366999
申请日:1980-12-17
Applicant: IBM
Inventor: HORNG CHENG T , MICHEL ALWIN E
IPC: H01L21/76 , H01L21/225 , H01L21/28 , H01L21/331 , H01L21/60 , H01L29/04 , H01L29/45 , H01L27/04 , H01L21/22
Abstract: CONSUMABLE AMORPHOUS OR POLYSILICON EMITTER PROCESS The process employs ion implantation for precise dopant control. The implantation is performed into a thin layer of amorphous silicon covering the emitter and collector opening. The implantation energy is chosen so that the damage is confined to the amorphous layer. Since the deposited silicon layer is to be removed by subsequent processing, its thickness must be carefully controlled. The layer is preferably deposited by a sputtering technique which allows the necessary uniformity and reproducibility of the layer thickness. Furthermore, the sputtering process with its energetic ions provides a reproducible quality interface which is of critical importance for a diffusion source. With such a source, the diffusion into the single crystal silicon extends about the same distance in the horizontal as the vertical direction. This provides the greatest possible horizontal displacement of the junction under the passivating silicon dioxide layer. The depths of the n-type region is thinned to the single crystal surface by consuming the polysilicon partly through oxidation and partly through conversion to platinum silicide. The platinum silicide silicon interface provides a high surface recombination velocity in order to deplete the density of holes injected into the emitter. The low hole density in the emitter region has a direct benefit of decreasing the switching delay due to hole storage in the emitter, and hence higher device performance. FI 9-79-062
-
公开(公告)号:CA1106981A
公开(公告)日:1981-08-11
申请号:CA312414
申请日:1978-09-29
Applicant: IBM
Inventor: HORNG CHENG T , MICHEL ALWIN E , RUPPRECHT HANS S , SCHWENKER ROBERT O
IPC: H01L29/73 , H01L21/033 , H01L21/265 , H01L21/331 , H01L21/76
Abstract: IMPROVED PROCESS FOR PRODUCING INTEGRATED CIRCUIT DEVICES BY ION IMPLANTATION In this process of producing a bipolar transistor, all the regions of the device except the emitter region are formed by ion implantation through an inorganic dielectric layer of uniform thickness. Subsequently, all the contact openings to the emitter, base and collector are formed and the emitter is implanted through the emitter contact opening. This unique combination of process steps permits the use of a surface insulating dielectric layer of uniform thickness, wherein all capacitances are uniform and controllable while still permitting direct implantation of the emitter, which, because of its shallow depth is difficult to implant through an oxide.
-
公开(公告)号:CA1142272A
公开(公告)日:1983-03-01
申请号:CA356128
申请日:1980-07-14
Applicant: IBM
Inventor: LEVER REGINALD F , MAUER JOHN L IV , MICHEL ALWIN E , ROTHMAN LAURA B
IPC: H01L21/76 , H01L21/31 , H01L21/312 , H01L21/316 , H01L21/762 , H01L21/26
Abstract: A PLANAR DEEP OXIDE ISOLATION PROCESS A planar deep oxide isolation process for providing deep wide silicon dioxide filled trenches in a planar surface of a silicon semiconductor substrate is described. The process comprises the steps of forming deep wide trenches in a planar surface of the silicon substrate; forming a thin layer of silicon dioxide on the planar surface of the silicon substrate and the exposed silicon surfaces of the deep wide trenches; applying resin glass (polysiloxane) to the planar surface of the semiconductor substrate and within the deep wide trenches; spinning off at least a portion of the resin glass on the planar surface of the substrate; baking the substrate at a low temperature; exposing the resin glass contained within the deep wide trenches of the substrate to the energy of an E-beam; developing the resin glass contained on said substrate in a solvent; heating the substrate in oxygen to convert the resin glass contained within the deep wide trenches to silicon dioxide; depositing a layer of silicon dioxide to provide a planar silicon dioxide surface on the exposed surface of the substrate; and planarize exposed silicon dioxide surface to silicon of substrate. FI9-79-011
-
公开(公告)号:CA834985A
公开(公告)日:1970-02-17
申请号:CA834985D
Applicant: IBM
Inventor: MICHEL ALWIN E , WALKER EDWARD J
-
-
-
-