公开(公告)号：CA1148269A

公开(公告)日：1983-06-14

申请号：CA372670

申请日：1981-03-10

Applicant: IBM

Inventor： HORNG CHENG T ,  KONIAN RICHARD R ,  SCHWENKER ROBERT O ,  WIEDER ARMIN W

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/8224 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/10 ,  H01L29/423 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L27/04 ,  H01L21/72

Abstract: Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer. FI 9-79-014

公开(公告)号：FR2344847A1

公开(公告)日：1977-10-14

申请号：FR7702072

申请日：1977-01-18

Applicant: IBM

Inventor： DEINES JOHN L ,  POPONIAK MICHAEL R ,  SCHWENKER ROBERT O

IPC: H01L21/66 ,  G01N27/00 ,  G01R31/26 ,  H01L21/306

公开(公告)号：CA1069221A

公开(公告)日：1980-01-01

申请号：CA272839

申请日：1977-02-28

Applicant: IBM

Inventor： DEINES JOHN L ,  POPONIAK MICHAEL R ,  SCHWENKER ROBERT O

IPC: H01L21/66 ,  G01N27/00 ,  G01R31/26 ,  H01L21/306

Abstract: ANODIC ETCHING METHOD FOR THE DETECTION OF ELECTRICALLY ACTIVE DEFECTS IN SILICON Electrically active defects, i.e., current-carrying defects or leakage paths in silicon crystals, are detected by an anodization process. The process selectively etches the crystal surface only where the electrically active defects are located when the anodization parameters are properly selected. Selected surface portions of the silicon structure are exposed to a hydrofluoric acid solution which is maintained at a negative potential with respect to the silicon structure. When the potential difference is set to a proper value, etch pits are formed in the surface of the silicon only at those locations overlying electrically active defects which impact device yield. The defects are observed and counted to provide a basis to predict yield of desired semiconductor devices to be formed later in the silicon structure.

公开(公告)号：FR2305853A1

公开(公告)日：1976-10-22

申请号：FR7603001

申请日：1976-01-29

Applicant: IBM

Inventor： KU SAN-MEI ,  PILLUS CHARLES A ,  POPONIAK MICHAEL R ,  SCHWENKER ROBERT O

IPC: C30B31/22 ,  H01L21/22 ,  H01L21/265 ,  H01L21/761

Abstract: In integrated circuit fabrication, a method is provided for simultaneously forming two regions of the same conductivity-type such as the base and isolation regions. In one embodiment, an epitaxial layer of one conductivity-type is formed on a substrate of opposite conductivity-type, after which dopant ions of the opposite conductivity-type are introduced into the epitaxial surface areas which are to provide the base and isolation regions, and in addition, the isolation regions are bombarded with non-dopant ions having a maximum atomic number of two, e.g., hydrogen or helium ion while the base regions are appropriately masked and remain umbombarded, said bombardment is carried out at temperatures below 300 DEG C, preferably room temperature. The bombardment is preferably carried out so that the non-dopant ions are implanted primarily in regions below the isolation regions. Next, the wafer is heated at a temperature at a range of from 600 DEG - 900 DEG C which is substantially below normal drive-in diffusion temperatures for unbombarded doped regions. The heating to be maintained for a period sufficient to drive-in diffuse the bombarded isolation regions through the epitaxial layer into contact with the substrate but is insufficient to drive-in the unbombarded base regions to such a depth.

公开(公告)号：CA1142266A

公开(公告)日：1983-03-01

申请号：CA360337

申请日：1980-09-16

Applicant: IBM

Inventor： HORNG CHENG T ,  POPONIAK MICHAEL R ,  RUPPRECHT HANS S ,  SCHWENKER ROBERT O

IPC: H01L21/76 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/73 ,  H01L29/732 ,  H01L27/04

Abstract: A SELF-ALIGNED MICROMETER BIPOLAR TRANSISTOR DEVICE AND PROCESS A method for fabricating very high performance integrated circuit semiconductor devices. The method for device fabrication disclosed is a self-aligned process. The device formed has small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls. The deep trench extends from the epitaxial silicon surface through N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3.0 .mu.m. A shallow oxide trench extending from the epitaxial silicon surface to the upper portion of the N+ subcollector separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. The fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in low collector-base capacitance which is a very important parameter in ultrahigh performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which surrounds the emitter and makes lateral contact to the active base. The P+ polysilicon layer which provides low base resistance is formed within the oxide isolation trenches, thus minimizing the parasitic capacitance. The transistor active base is formed in place by a low dosage boron implantation made with its concentration peak below the emitter. The device formed thus will have a controllable narrow base width and a FI9-79-021 low external base resistance. Both are essential to the high performance devices. The emitter of this invention structure is separated from the P+ polysilicon by a Si3N4/SiO2 composite dielectric layer. This dielectric separation ensures that electrons injected into the base do occur at the bottom of the emitter. The dielectric sleeve of the emitter also eliminates the sidewall hole current component normally existing in conventional transistors. Thus, the bipolar transistors formed by the disclosed process have a high emitter injection efficiency and also have high transistor current gains. Furthermore, the fabricated small geometry devices have planarized surface. The planarized device structure ensures the thin film covering which is critical to the integration of very small devices. FI 9-79-021

公开(公告)号：CA1043474A

公开(公告)日：1978-11-28

申请号：CA289545

申请日：1977-10-26

Applicant: IBM

Inventor： RUPPRECHT HANS S ,  SCHWENKER ROBERT O

IPC: H01L29/73 ,  G01Q70/00 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/331 ,  H01L21/78 ,  H01L21/461 ,  H01L21/425

Abstract: A METHOD OF HIGH CURRENT ION IMPLANTATION A method of ion implantation is provided which is particularly applicable to the fabrication of integrated circuits with high current ion implantation apparatus utilizing ion beams having currents of at least 0.5 ma. The method avoids excessive charge buildup on semiconductor wafer surfaces which may destroy the surface electrical insulation, thereby rendering the integrated circuit ineffective. The method involves forming in a layer of electrically insulative material over the wafer, a plurality of openings through the insulative layer in the various chip areas to expose the semiconductor wafer surfaces which are to be ion implanted with conductivity-determining impurities, and in addition, forming openings through the insulative layer over the kerf area between wafer chips to expose wafer kerf adjacent to the chip openings. The total area exposed in the wafer kerf must be greater than the total area exposed in said chip wafer openings. Then, a beam of ions having sufficient energy to implant ions in the exposed wafer in said chip area and kerf openings is directed at the wafer. The presence of the kerf openings avoids the problem of charge buildup. Then, the kerf area is removed by conventional dicing to separate the wafer into a plurality of chips.

公开(公告)号：FR2379163A1

公开(公告)日：1978-08-25

申请号：FR7739913

申请日：1977-12-23

Applicant: IBM

Inventor： RUPPRECHT HANS S ,  SCHWENKER ROBERT O

IPC: H01L29/73 ,  G01Q70/00 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/331 ,  H01L21/78

Abstract: A method of ion implantation is provided which is particularly applicable to the fabrication of integrated circuits with high current ion implantation apparatus utilizing ion beams having currents of at least 0.5 ma. The method avoids excessive charge buildup on semiconductor wafer surfaces which may destroy the surface electrical insulation, thereby rendering the integrated circuit ineffective. The method involves forming in a layer of electrically insulative material over the wafer, a plurality of openings through the insulative layer in the various chip areas to expose the semiconductor wafer surfaces which are to be ion implanted with conductivity-determining impurities, and in addition, forming openings through the insulative layer over the kerf area between wafer chips to expose wafer kerf adjacent to the chip openings. The total area exposed in the wafer kerf must be greater than the total area exposed in said chip wafer openings. Then, a beam of ions having sufficient energy to implant ions in the exposed wafer in said chip area and kerf openings is directed at the wafer. The presence of the kerf openings avoids the problem of charge buildup. Then, the kerf area is removed by conventional dicing to separate the wafer into a plurality of chips.

公开(公告)号：CA1139017A

公开(公告)日：1983-01-04

申请号：CA349765

申请日：1980-04-14

Applicant: IBM

Inventor： HORNG CHENG T ,  SCHWENKER ROBERT O

IPC: H01L21/76 ,  H01L21/033 ,  H01L21/263 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/762 ,  H01L21/768

Abstract: A semiconductor substrate is selectively etched to produce a spaced succession of narrow, shallow trenches separated by narrow silicon mesas. Silicon oxide is chemical-vapor-deposited on the horizontal and vertical surfaces of the etched structure to a thickness equalling the width of a desired silicon oxide mask. The mask is used for etching multiple deep trenches in the substrate, the trenches being separated by thin walls of silicon. The thickness of the walls is uniformly equal to and determined by the thickness of the deposited silicon oxide mask. The deposited silicon oxide is reactively ion etched away from the horizontal surfaces, leaving the oxide only on the sidewalls of the shallow trenches. The silicon is deeply etched, using the remaining oxide as a mask. Boron is ion implanted and the resulting structure is thermally oxidized sufficiently to completely oxidize the silicon under the deposited oxide mask and to oxidize the silicon surfaces at the bottoms of the trenches. The remaining trench volume is filled in with chemical-vapor-deposited silicon dioxide.

公开(公告)号：CA1106981A

公开(公告)日：1981-08-11

申请号：CA312414

申请日：1978-09-29

Applicant: IBM

Inventor： HORNG CHENG T ,  MICHEL ALWIN E ,  RUPPRECHT HANS S ,  SCHWENKER ROBERT O

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/265 ,  H01L21/331 ,  H01L21/76

Abstract: IMPROVED PROCESS FOR PRODUCING INTEGRATED CIRCUIT DEVICES BY ION IMPLANTATION In this process of producing a bipolar transistor, all the regions of the device except the emitter region are formed by ion implantation through an inorganic dielectric layer of uniform thickness. Subsequently, all the contact openings to the emitter, base and collector are formed and the emitter is implanted through the emitter contact opening. This unique combination of process steps permits the use of a surface insulating dielectric layer of uniform thickness, wherein all capacitances are uniform and controllable while still permitting direct implantation of the emitter, which, because of its shallow depth is difficult to implant through an oxide.

公开(公告)号：FR2316732A1

公开(公告)日：1977-01-28

申请号：FR7616133

申请日：1976-05-21

Applicant: IBM

Inventor： POPONIAK MICHAEL R ,  SCHWENKER ROBERT O

IPC: H01L21/316 ,  H01L21/762 ,  H01L21/76

Abstract: In the fabrication of integrated circuits, a method is provided for forming dielectrically isolated regions in a semiconductor substrate comprising forming over the semiconductor substrate surface an electrically insulating layer of dielectric material having a plurality of openings therethrough and etching to form recesses in the semiconductor substrate exposed in the openings. Then, aluminum is deposited over the substrate so that an aluminum layer is formed on said layer of dielectric material as well as in said recesses. Next, the aluminum in the recesses is selectively anodized to form aluminum oxide, and the remaining aluminum on said layer of dielectric material is removed either by selectively etching away the aluminum layer or by a "lift-off" technique wherein the insulating layer of dielectric material under the aluminum is etched away thereby "lifting-off" and removing the aluminum.