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    CONSUMABLE AMORPHOUS OR POLYSILICON EMITTER PROCESS
    1.
    发明专利
    CONSUMABLE AMORPHOUS OR POLYSILICON EMITTER PROCESS 未知

    公开(公告)号：CA1148273A

    公开(公告)日：1983-06-14

    申请号：CA366999

    申请日：1980-12-17

    Applicant: IBM

    Inventor： HORNG CHENG T ,  MICHEL ALWIN E

    IPC: H01L21/76 ,  H01L21/225 ,  H01L21/28 ,  H01L21/331 ,  H01L21/60 ,  H01L29/04 ,  H01L29/45 ,  H01L27/04 ,  H01L21/22

    Abstract: CONSUMABLE AMORPHOUS OR POLYSILICON EMITTER PROCESS The process employs ion implantation for precise dopant control. The implantation is performed into a thin layer of amorphous silicon covering the emitter and collector opening. The implantation energy is chosen so that the damage is confined to the amorphous layer. Since the deposited silicon layer is to be removed by subsequent processing, its thickness must be carefully controlled. The layer is preferably deposited by a sputtering technique which allows the necessary uniformity and reproducibility of the layer thickness. Furthermore, the sputtering process with its energetic ions provides a reproducible quality interface which is of critical importance for a diffusion source. With such a source, the diffusion into the single crystal silicon extends about the same distance in the horizontal as the vertical direction. This provides the greatest possible horizontal displacement of the junction under the passivating silicon dioxide layer. The depths of the n-type region is thinned to the single crystal surface by consuming the polysilicon partly through oxidation and partly through conversion to platinum silicide. The platinum silicide silicon interface provides a high surface recombination velocity in order to deplete the density of holes injected into the emitter. The low hole density in the emitter region has a direct benefit of decreasing the switching delay due to hole storage in the emitter, and hence higher device performance. FI 9-79-062

    PROCESS FOR MAKING LARGE AREA ISOLATION TRENCHES
    2.
    发明专利
    PROCESS FOR MAKING LARGE AREA ISOLATION TRENCHES 未知

    公开(公告)号：CA1139017A

    公开(公告)日：1983-01-04

    申请号：CA349765

    申请日：1980-04-14

    Applicant: IBM

    Inventor： HORNG CHENG T ,  SCHWENKER ROBERT O

    IPC: H01L21/76 ,  H01L21/033 ,  H01L21/263 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/762 ,  H01L21/768

    Abstract: A semiconductor substrate is selectively etched to produce a spaced succession of narrow, shallow trenches separated by narrow silicon mesas. Silicon oxide is chemical-vapor-deposited on the horizontal and vertical surfaces of the etched structure to a thickness equalling the width of a desired silicon oxide mask. The mask is used for etching multiple deep trenches in the substrate, the trenches being separated by thin walls of silicon. The thickness of the walls is uniformly equal to and determined by the thickness of the deposited silicon oxide mask. The deposited silicon oxide is reactively ion etched away from the horizontal surfaces, leaving the oxide only on the sidewalls of the shallow trenches. The silicon is deeply etched, using the remaining oxide as a mask. Boron is ion implanted and the resulting structure is thermally oxidized sufficiently to completely oxidize the silicon under the deposited oxide mask and to oxidize the silicon surfaces at the bottoms of the trenches. The remaining trench volume is filled in with chemical-vapor-deposited silicon dioxide.

    PROCESS FOR PRODUCING INTEGRATED CIRCUIT DEVICES BY ION IMPLANTATION
    3.
    发明专利
    PROCESS FOR PRODUCING INTEGRATED CIRCUIT DEVICES BY ION IMPLANTATION 未知

    公开(公告)号：CA1106981A

    公开(公告)日：1981-08-11

    申请号：CA312414

    申请日：1978-09-29

    Applicant: IBM

    Inventor： HORNG CHENG T ,  MICHEL ALWIN E ,  RUPPRECHT HANS S ,  SCHWENKER ROBERT O

    IPC: H01L29/73 ,  H01L21/033 ,  H01L21/265 ,  H01L21/331 ,  H01L21/76

    Abstract: IMPROVED PROCESS FOR PRODUCING INTEGRATED CIRCUIT DEVICES BY ION IMPLANTATION In this process of producing a bipolar transistor, all the regions of the device except the emitter region are formed by ion implantation through an inorganic dielectric layer of uniform thickness. Subsequently, all the contact openings to the emitter, base and collector are formed and the emitter is implanted through the emitter contact opening. This unique combination of process steps permits the use of a surface insulating dielectric layer of uniform thickness, wherein all capacitances are uniform and controllable while still permitting direct implantation of the emitter, which, because of its shallow depth is difficult to implant through an oxide.

    SELF-ALIGNED MICROMETER BIPOLAR TRANSISTOR DEVICE AND PROCESS
    4.
    发明专利
    SELF-ALIGNED MICROMETER BIPOLAR TRANSISTOR DEVICE AND PROCESS 未知

    公开(公告)号：CA1142266A

    公开(公告)日：1983-03-01

    申请号：CA360337

    申请日：1980-09-16

    Applicant: IBM

    Inventor： HORNG CHENG T ,  POPONIAK MICHAEL R ,  RUPPRECHT HANS S ,  SCHWENKER ROBERT O

    IPC: H01L21/76 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/73 ,  H01L29/732 ,  H01L27/04

    Abstract: A SELF-ALIGNED MICROMETER BIPOLAR TRANSISTOR DEVICE AND PROCESS A method for fabricating very high performance integrated circuit semiconductor devices. The method for device fabrication disclosed is a self-aligned process. The device formed has small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls. The deep trench extends from the epitaxial silicon surface through N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3.0 .mu.m. A shallow oxide trench extending from the epitaxial silicon surface to the upper portion of the N+ subcollector separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. The fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in low collector-base capacitance which is a very important parameter in ultrahigh performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which surrounds the emitter and makes lateral contact to the active base. The P+ polysilicon layer which provides low base resistance is formed within the oxide isolation trenches, thus minimizing the parasitic capacitance. The transistor active base is formed in place by a low dosage boron implantation made with its concentration peak below the emitter. The device formed thus will have a controllable narrow base width and a FI9-79-021 low external base resistance. Both are essential to the high performance devices. The emitter of this invention structure is separated from the P+ polysilicon by a Si3N4/SiO2 composite dielectric layer. This dielectric separation ensures that electrons injected into the base do occur at the bottom of the emitter. The dielectric sleeve of the emitter also eliminates the sidewall hole current component normally existing in conventional transistors. Thus, the bipolar transistors formed by the disclosed process have a high emitter injection efficiency and also have high transistor current gains. Furthermore, the fabricated small geometry devices have planarized surface. The planarized device structure ensures the thin film covering which is critical to the integration of very small devices. FI 9-79-021

    POLYSILICON-BASE SELF-ALIGNED BIPOLAR TRANSISTOR PROCESS AND STRUCTURE
    6.
    发明专利
    POLYSILICON-BASE SELF-ALIGNED BIPOLAR TRANSISTOR PROCESS AND STRUCTURE 未知

    公开(公告)号：CA1153830A

    公开(公告)日：1983-09-13

    申请号：CA370960

    申请日：1981-02-16

    Applicant: IBM

    Inventor： HO ALLEN P ,  HORNG CHENG T

    IPC: H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L29/417 ,  H01L29/732 ,  H01L21/70

    Abstract: A POLYSILICON-BASE SELF-ALIGNED BIPOLAR TRANSISTOR PROCESS AND STRUCTURE of The Disclosure Disclosed is a process for forming an improved bipolar transistor in a silicon substrate of a first conductivity type, said silicon substrate having a planar surface, a subcollector region of a second conductivity type formed in said substrate, an epitaxial layer of said second conductivity type formed on said planar surface or said substrate, and first, second and third spaced apart recessed oxide isolation regions extending from the planar surface of said epitaxial layer into said substrate, a subcollector reach-through region positioned between said second and third recessed oxide isolation regions, said subcollector reach-through region extending from said planar surface of said epitaxial layer to said subcollector region, said process including the following steps: deposit, using chemical vapor deposition techniques, a layer of doped polysilicon on the exposed surface of said substrate said dopant being of said first conductivity type; deposit, using chemical vapor deposition techniques a first layer of silicon dioxide on said polysilicon layer; deposit a layer of photoresist on said first layer of silicon dioxide; utilizing photolithography, mask off an intended intrinsic base region, said intended intrinsic base region being spaced between said first and second recessed oxide isolation regions; utilizing the resist layer as a mask employ reactive ion etching to remove the silicon dioxide and polysilicon superimposed over the intended intrinsic base region; ion implant the exposed intrinsic base region with ions of said first conductivity type; chemically vapor deposit a relatively thick silicon dioxide conformal coating on the FI 9-79-022 exposed surface; reactive ion etch an emitter opening on the epitaxial surface above the implanted intrinsic base; ion implant the emitter region with ions of said second conductivity type; and utilize a single heat cycle to anneal the ion implantations and drive in the emitter, intrinsic base, extrinsic base and collector reach through. FI 9-79-022

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