公开(公告)号：EP1905074A4

公开(公告)日：2012-06-27

申请号：EP06773946

申请日：2006-06-26

Applicant: IBM

Inventor： BRYANT ANDRES ,  NOWAK EDWARD J ,  WILLIAMS RICHARD Q

IPC: H01L21/84 ,  H01L27/108 ,  H01L29/786

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0811 ,  H01L28/40 ,  H01L29/78648 ,  Y10T436/235 ,  Y10T436/25125 ,  Y10T436/2525 ,  Y10T436/25375

公开(公告)号：EP2401761A4

公开(公告)日：2012-04-25

申请号：EP10780978

申请日：2010-05-04

Applicant: IBM

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

IPC: H01L21/8244 ,  H01L21/8234 ,  H01L27/11

CPC classification number: H01L27/0207 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1104

公开(公告)号：WO03001604A2

公开(公告)日：2003-01-03

申请号：PCT/EP0206202

申请日：2002-06-06

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： BRYANT ANDRES ,  IEONG MEIKEI ,  MULLER K PAUL ,  NOWAK EDWARD J ,  FRIED DAVID M ,  RANKIN JED

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/28

CPC classification number: H01L29/4908 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785

Abstract: Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and -0.5V for pFETs.

Abstract translation: 因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。 本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。 通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。 特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。 例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。

公开(公告)号：EP1639648A4

公开(公告)日：2007-05-30

申请号：EP04777432

申请日：2004-06-30

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

IPC: H01L29/06 ,  H01L21/00 ,  H01L21/308 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/76 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin (100), and a second-type of FinFET which includes a second fin (102) running parallel to the first fin (100). The invention also has an insulator fin positioned between the source/drain regions (130) of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin (100) and the second fin (102), such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate (106) formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate (106) includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin (100) and the second fin (102) have approximately the same width.

公开(公告)号：EP2281303A4

公开(公告)日：2013-11-20

申请号：EP09798429

申请日：2009-06-18

Applicant: IBM

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/334 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: A design structure is provided for spacer fill structures and, more particularly, spacer fill structures, a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip.

公开(公告)号：EP1692724A4

公开(公告)日：2007-11-21

申请号：EP03796818

申请日：2003-12-08

Applicant: IBM

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

IPC: H01L27/148 ,  H01L21/336 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1211 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit semiconductor memory device (100) has a first dielectric layer (116) characterized as the BOX layer absent from a portion (130) of the substrate (112) under the gate of a storage transistor to increase the gate-to-substrate capacitance and thereby reduce the soft error rate. A second dielectric layer (132) having a property different from the first dielectric layer at least partly covers that portion (130) of the substrate. The device may be a FinFET device including a fin (122) and a gate dielectric layer (124, 126) between the gate and the fin, with the second dielectric layer having less leakage than the gate dielectric layer.

公开(公告)号：JP2002314094A

公开(公告)日：2002-10-25

申请号：JP2002052160

申请日：2002-02-27

Applicant: IBM

Inventor： BRYANT ANDRES ,  LASKY JEROME B ,  EDWARD J NOWACK ,  RANKIN JED H ,  MIN H TON

IPC: H01L29/43 ,  H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/08 ,  H01L27/11 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for avoiding a floating body effect in an SOI structure. SOLUTION: A semiconductor device includes SOI FETs which include silicon bodies on an insulating layer on a conductive substrate. Gate dielectrics and gates are formed on the surfaces of the silicon bodies, and sources and drains are formed on two sides of the gates. Buried body contacts to substrate conductors are formed under the third side of the gate. The buried body contacts do not extend to the upper face of the silicon bodies. The buried body contacts are separated from the gates by second dielectrics whose thicknesses are generally larger than the thicknesses of the first gate dielectrics. The buried body contacts are plugs made of conductive materials, and the second dielectrics cover the body contacts under the gates. The FETs can be used in a SRAM circuit or any other type of circuit having the silicon on insulator(SOI) structure.

公开(公告)号：JP2005317978A

公开(公告)日：2005-11-10

申请号：JP2005131256

申请日：2005-04-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BRYANT ANDRES ,  OMER H DOKUMACI ,  HANAFI HUSSEIN I ,  EDWARD J NOWAKU

IPC: H01L21/265 ,  H01L21/00 ,  H01L21/335 ,  H01L21/336 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/42368 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/7856

Abstract: PROBLEM TO BE SOLVED: To provide a method to generate a FinFET with a back gate, which has dielectric layers whose thicknesses are different on its front gate side and back gate side.
SOLUTION: Several steps are included to introduce impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. Impurities that can be introduced through implantation may enhance or retard dielectric formation.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种产生具有背栅的FinFET的方法，其具有在其前栅极侧和后栅极侧的厚度不同的电介质层。 解决方案：包括几个步骤以将杂质引入FinFET的鳍的至少一侧，以形成具有不同厚度的电介质层。 可以通过植入引入的杂质可以增强或延缓电介质形成。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2003008428A

公开(公告)日：2003-01-10

申请号：JP2002116448

申请日：2002-04-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： BRYANT ANDRES ,  COTTRELL PETER EDWIN ,  ELLIS-MONAGHAN JOHN JOSEPH ,  KETCHEN MARK B ,  NOWAK EDWARD J

IPC: H01L27/04 ,  G05F3/20 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K19/094

CPC classification number: G05F3/205 ,  H01L27/0218

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus for biasing ultra-low voltage logic circuits.
SOLUTION: An integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply and second power supply or ground. The gate and source of the first transistor are connected to the second power supply. The drains and bodies of the first and second transistors are connected to form an output connected to the bodies of the other transistors within the integrated circuit device.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种用于偏压超低电压逻辑电路的装置。 解决方案：集成电路器件包括多个晶体管和全局体偏置电路。 全局体偏置电路包括串联连接在电源和第二电源或地之间的第一晶体管和第二晶体管。 第一晶体管的栅极和源极连接到第二电源。 第一和第二晶体管的漏极和主体被连接以形成连接到集成电路器件内的其它晶体管的主体的输出端。

公开(公告)号：WO2013101790A3

公开(公告)日：2015-06-11

申请号：PCT/US2012071579

申请日：2012-12-24

Applicant: IBM

Inventor： BRYANT ANDRES ,  BASKER VEERARAGHAVAN S ,  BU HUIMING ,  HAENSCH WILFRIED ,  LEOBANDUNG EFFENDI ,  LIN CHUNG-HSUN ,  STANDAERT THEORDORUS E ,  YAMASHITA TENKO ,  YEH CHUN-CHEN

IPC: H01L21/00

CPC classification number: H01L29/41791 ,  H01L29/66795

Abstract: A method is provided for fabricating a finFET device. Fin structures are formed over a BOX layer. The fin structures include a semiconductor layer and extend in a first direction. A gate stack is formed on the BOX layer over the fin structures and extending in a second direction. The gate stack includes a high-K dielectric layer and a metal gate. Gate spacers are formed on sidewalls of the gate stack, and an epi layer is deposited to merge the fin structures. Ions are implanted to form source and drain regions, and dummy spacers are formed on sidewalls of the gate spacers. The dummy spacers are used as a mask to recess or completely remove an exposed portion of the epi layer. Silicidation forms silicide regions that abut the source and drain regions and each include a vertical portion located on the vertical sidewall of the source or drain region.

Abstract translation: 提供了一种用于制造finFET器件的方法。 翅片结构形成在BOX层上。 翅片结构包括半导体层并沿第一方向延伸。 栅极叠层形成在鳍状结构上的BOX层上并沿第二方向延伸。 栅极堆叠包括高K电介质层和金属栅极。 栅极间隔物形成在栅极堆叠的侧壁上，并且沉积外延层以使翅片结构合并。 植入离子以形成源极和漏极区，并且在栅极间隔物的侧壁上形成虚设间隔物。 虚拟间隔物用作掩模以凹进或完全去除外延层的暴露部分。 硅化形成邻接源极和漏极区域的硅化物区域，并且每个都包括位于源极或漏极区域的垂直侧壁上的垂直部分。