公开(公告)号：JP2003249622A

公开(公告)日：2003-09-05

申请号：JP2003019022

申请日：2003-01-28

Applicant: IBM

Inventor： LASKY JEROME B ,  NOWAK EDWARD J ,  SPROGIS EDMUND J

IPC: H01L25/18 ,  H01L21/768 ,  H01L23/48 ,  H01L23/50 ,  H01L25/065 ,  H01L25/07

Abstract: PROBLEM TO BE SOLVED: To provide chip-on-chip module and a forming method belonging to the same. SOLUTION: A first semiconductor chip is connected to a second semiconductor chip. The first chip comprises a first wiring layer and a first conductive substrate in the first side and the second side of the first chip, respectively. A power supply voltage VDD is adapted so as to be electrically connected to the second side of the first chip. The second chip comprises a second wiring layer and a second conductive substrate in the first side and the second side of the second chip, respectively. A grounding voltage GND is adapted so as to be electrically connected to the second side of the second chip. The first side of the first chip is connected to the first side of the second chip. The power supply voltage VDD and the grounding voltage GND are adapted so as to supply an electric power to the first and the second chips. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2002314094A

公开(公告)日：2002-10-25

申请号：JP2002052160

申请日：2002-02-27

Applicant: IBM

Inventor： BRYANT ANDRES ,  LASKY JEROME B ,  EDWARD J NOWACK ,  RANKIN JED H ,  MIN H TON

IPC: H01L29/43 ,  H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/08 ,  H01L27/11 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for avoiding a floating body effect in an SOI structure. SOLUTION: A semiconductor device includes SOI FETs which include silicon bodies on an insulating layer on a conductive substrate. Gate dielectrics and gates are formed on the surfaces of the silicon bodies, and sources and drains are formed on two sides of the gates. Buried body contacts to substrate conductors are formed under the third side of the gate. The buried body contacts do not extend to the upper face of the silicon bodies. The buried body contacts are separated from the gates by second dielectrics whose thicknesses are generally larger than the thicknesses of the first gate dielectrics. The buried body contacts are plugs made of conductive materials, and the second dielectrics cover the body contacts under the gates. The FETs can be used in a SRAM circuit or any other type of circuit having the silicon on insulator(SOI) structure.

公开(公告)号：JPS61296709A

公开(公告)日：1986-12-27

申请号：JP14039686

申请日：1986-06-18

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  LASKY JEROME B ,  NESBIT LARRY A ,  SEDGWICK THOMAS O ,  STIFFLER SCOTT R

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/316 ,  H01L21/84 ,  H01L27/12

公开(公告)号：CA1209280A

公开(公告)日：1986-08-05

申请号：CA485177

申请日：1985-06-25

Applicant: IBM

Inventor： KINNEY WAYNE I ,  KOBURGER CHARLES W III ,  LASKY JEROME B ,  NESBIT LARRY A ,  TROUTMAN RONALD R ,  WHITE FRANCIS R

IPC: H01L27/08 ,  H01L21/033 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

Abstract: PROCESS OF MAKING DUAL WELL CMOS SEMICONDUCTOR STRUCTURE WITH ALIGNED FIELD-DOPINGS USING SINGLE MASKING STEP A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implanation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the wells so that, with a subsequent masking step, oxide field isolations are defined over the doped oxide layers. A heat cycle is then used to drive the field dopants into the corresponding field-doping regions.

公开(公告)号：CA1247259A

公开(公告)日：1988-12-20

申请号：CA556671

申请日：1988-01-15

Applicant: IBM

Inventor： LASKY JEROME B

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/764 ,  H01L27/12 ,  H01L21/08 ,  B24B1/00 ,  H01L21/302

Abstract: A method of improving silicon-on-insulator uniformity using polishing. A polishing stop layer of substantially uniform thickness is provided having a first side which is made coplanar with a first side of a thicker layer of semiconductor material. A polishing process is applied to a second side of the semiconductor material until a second side of the polishing stop layer is encountered, such that the substantially uniform thickness of the polishing stop layer can be used to define the semiconductor material to a layer of uniform thickness.

公开(公告)号：CA1189768A

公开(公告)日：1985-07-02

申请号：CA404043

申请日：1982-05-28

Applicant: IBM

Inventor： HANSEN HOWARD H ,  LASKY JEROME B ,  SILVERMAN RONALD R

IPC: H01L21/265 ,  H01L21/268 ,  H01L21/74 ,  H01L21/428

Abstract: A METHOD OF LASER ANNEALING OF SUBSURFACE ION IMPLANTED REGIONS A method for annealing ion implanted regions buried in a semiconductor substrate without the undesirable effects of thermal diffusion which includes the radiation of the substrate by a continuous laser having an emission frequency longer than 600 nanometers which the buried ion implanted regions will absorb strongly but which will be substantially unabsorbed by the unimplanted regions. Superior results can be obtained when the substrate is heated to approximately 300.degree. during this laser annealing.

公开(公告)号：SG77259A1

公开(公告)日：2000-12-19

申请号：SG1999003558

申请日：1999-07-17

Applicant: IBM

Inventor： ALLEN ARCHIBALD ,  WHITE FRANCIS R ,  RANKIN JED H ,  MANN RANDY W ,  LASKY JEROME B

IPC: H01L21/285 ,  H01L21/28 ,  H01L21/311

Abstract: A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.

公开(公告)号：CA1218762A

公开(公告)日：1987-03-03

申请号：CA495661

申请日：1985-11-19

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  LASKY JEROME B ,  NESBIT LARRY A ,  SEDGWICK THOMAS O ,  STIFFLER SCOTT R

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/316 ,  H01L21/84 ,  H01L27/12 ,  H01L21/306

Abstract: A method of forming a thin silicon layer upon which semiconductor devices may be constructed. An epitaxial layer is grown on a silicon substrate, and oxygen or nitrogen ions are implanted into the epitaxial layer in order to form a buried etch-stop layer therein. An oxide layer is grown on the epitaxial layer, and is used to form a bond to a mechanical support wafer. The silicon substrate is removed using grinding and/or HNA, the upper portions of the epitaxy are removed using EDP, EPP or KOH, and the etch-stop is removed using a non-selective etch. The remaining portions of the epitaxy forms the thin silicon layer. Due to the uniformity of the implanted ions, the thin silicon layer has a very uniform thickness. BU9-84-031