公开(公告)号：GB2600871A

公开(公告)日：2022-05-11

申请号：GB202201893

申请日：2020-08-17

Applicant: IBM

Inventor： XIAO SUN ,  JUNGWOOK CHOI ,  NAIGANG WANG ,  CHIA-YU CHEN ,  KAILASH GOPALAKRISHNAN

IPC: G06N3/08

Abstract: An apparatus for training and inferencing a neural network includes circuitry that is configured to generate a first weight having a first format including a first number of bits based at least in part on a second weight having a second format including a second number of bits and a residual having a third format including a third number of bits. The second number of bits and the third number of bits are each less than the first number of bits. The circuitry is further configured to update the second weight based at least in part on the first weight and to update the residual based at least in part on the updated second weight and the first weight. The circuitry is further configured to update the first weight based at least in part on the updated second weight and the updated residual.

公开(公告)号：GB2577196A

公开(公告)日：2020-03-18

申请号：GB201916879

申请日：2018-05-14

Applicant: IBM

Inventor： RAJIV V JOSHI ,  NAIGANG WANG ,  BRUCE DORIS

IPC: H02M3/158

Abstract: Circuits and methods are disclosed for providing a supply voltage to a dynamic internal power supply node of a group of other circuits. A circuit includes a first transistor and a second transistor, of different channel types, coupled in parallel to a static power supply that supplies a constant power supply voltage. The circuit further includes a magnetic inductor having a first terminal connected to a common node between the first transistor and the second transistor and a second terminal connected to the dynamic internal power supply node, to supply the dynamic internal power supply node with a boosted voltage having a magnitude greater than a magnitude of the constant power supply voltage by resonating with at least one capacitance coupled to the dynamic internal power supply node.

公开(公告)号：GB2577210B

公开(公告)日：2022-05-11

申请号：GB201917541

申请日：2018-05-31

Applicant: IBM

Inventor： RAJIV V JOSHI ,  NAIGANG WANG ,  BRUCE DORIS

IPC: H03B5/08 ,  H03B1/04

Abstract: Semiconductor devices and methods relating to the semiconductor devices are provided. A semiconductor device includes a resonant clock circuit. The semiconductor device further includes an inductor. The semiconductor device also includes a magnetic layer formed of a magnetic material disposed in between a portion of the resonant clock circuit and the inductor. Clock signals of the resonant clock circuit are utilized by the magnetic layer.

公开(公告)号：GB2577210A

公开(公告)日：2020-03-18

申请号：GB201917541

申请日：2018-05-31

Applicant: IBM

Inventor： RAJIV V JOSHI ,  NAIGANG WANG ,  BRUCE DORIS

IPC: H03K5/00

Abstract: Semiconductor devices and methods relating to the semiconductor devices are provided. A semiconductor device includes a resonant clock circuit. The semiconductor device further includes an inductor. The semiconductor device also includes a magnetic layer formed of a magnetic material disposed in between a portion of the resonant clock circuit and the inductor. Clock signals of the resonant clock circuit are utilized by the magnetic layer.

公开(公告)号：GB2566664A8

公开(公告)日：2019-03-27

申请号：GB201901265

申请日：2017-06-13

Applicant: IBM

Inventor： HARIKLIA DELIGIANNI ,  EUGENE O'SULLIVAN ,  NAIGANG WANG ,  BRUCE DORIS

IPC: H01F17/00 ,  H01L23/522

Abstract: A magnetic laminating structure includes alternating layers of a magnetic material (112) and a multilayered insulating material, wherein the multilayered insulating material is intermediate adjacent magnetic material layers and comprises a first insulating layer (114A) abutting at least on additional insulating layer (114B), and wherein the first insulating layer (114A) and the at least one additional insulating layer (114B) comprise different dielectric materials and/or are formed by a different deposition process.

公开(公告)号：GB2566664A

公开(公告)日：2019-03-20

申请号：GB201901265

申请日：2017-06-13

Applicant: IBM

Inventor： HARIKLIA DELIGIANNI ,  EUGENE O'SULLIVAN ,  NAIGANG WANG ,  BRUCE DORIS

IPC: H01F17/00 ,  H01L23/522

Abstract: A magnetic laminating structure includes alternating layers of a magnetic material (112) and a multilayered insulating material, wherein the multilayered insulating material is intermediate adjacent magnetic material layers and comprises a first insulating layer (114A) abutting at least on additional insulating layer (114B), and wherein the first insulating layer (114A) and the at least one additional insulating layer (114B) comprise different dielectric materials and/or are formed by a different deposition process.

公开(公告)号：GB2566664B

公开(公告)日：2020-03-11

申请号：GB201901265

申请日：2017-06-13

Applicant: IBM

Inventor： HARIKLIA DELIGIANNI ,  EUGENE O'SULLIVAN ,  NAIGANG WANG ,  BRUCE DORIS

IPC: H01F17/00 ,  H01L23/522

Abstract: A magnetic laminating structure and process includes alternating layers of a magnetic material and a multilayered insulating material, wherein the multilayered insulating material is intermediate adjacent magnetic material layers and comprises a first insulating layer abutting at least one additional insulating layer, wherein the first insulating layer and the at least one additional insulating layer comprise different dielectric materials and/or are formed by a different deposition process, and wherein the layers of the magnetic material have a cumulative thickness greater than 1 micron.

公开(公告)号：GB2536814A

公开(公告)日：2016-09-28

申请号：GB201604426

申请日：2016-03-16

Applicant: IBM

Inventor： HARIKLIA DELIGIANNI ,  NAIGANG WANG ,  LUBOMYR ROMANKIW ,  WILLIAM JOSEPH GALLAGHER ,  ANDREW JOHN KELLOCK ,  EUGENE O'SULLIVAN

IPC: H01L43/02 ,  C23C18/16 ,  C23C18/50 ,  H01F41/24 ,  H01L21/288 ,  H01L43/12

Abstract: An on-chip (on die) magnetic structure manufactured on a semiconductor (Si, GaAs, SiC) substrate 110, comprising (in sequence from substrate) an adhesive layer 120 upon which is deposited a Ni, Co, Pd or Cu seed layer 130 which has been further activated by immersion in a palladium Pd rich solution, to form a thin Pd nanoparticle over-layer 510. The cobalt-tungsten-phosphorus layer 610 is deposited by electroless plating on the palladium rich seed layer 510, 130 to form a high electrical resistivity Pd/CoWP magnetic layer 610/510 (620). The layers may be conventionally defined by photolithography. The magnetic material 620 comprises cobalt Co in a range 80 - 90 atomic percent (at. %) based on the total number of atoms of the magnetic material, tungsten (W) in a range from 4 to 9 atomic percent, and phosphorous (P) in a range from 7 to 15 atomic percent, (and more preferably 9 to 11 at%), the material further comprising palladium Pd dispersed throughout the magnetic material. The Palladium comprising Cobalt-Tungsten-Phosphorus (Pd + CoWP or Pd/CoWP) magnetic material 620 is preferably amorphous. The on chip magnetic structure resistivity is in excess of 100 µΩ.cm. The on chip magnetic structure may be a magnetic yoke, slab, inductor or transformer. The magnetic seed layer may be at least 40nm thick, the Pd-CoWP magnetic layer 620 having thickness 200nm to 1200nm (1.2µm). Applications for the magnetic structure may include miniature power converters.