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公开(公告)号：JP2001308345A
公开(公告)日：2001-11-02
申请号：JP2001090670
申请日：2001-03-27
Applicant: IBM
Inventor： PAUL STEVEN ANDREE , COLGAN EVAN GEORGE , JOHN C FLAKE , PETER FRYER , WILLIAM GRAHAM , EUGENE O'SULLIVAN
IPC: H01L21/28 , H01L21/225 , H01L21/336 , H01L29/417 , H01L29/45 , H01L29/786
Abstract: PROBLEM TO BE SOLVED: To provide a method for simplifying formation of an ohmic contact for a thin film transistor. SOLUTION: The method for forming an ohmic contact for a semiconductor device includes a step of forming a metal-contained layer containing integrally formed dopants. The metal-contained layer is patterned to form a constituent element of the semiconductor device, and a semiconductor layer is deposited in contact with the metal-contained layer. The semiconductor device is annealed so that dopants are outwardly diffused from the metal-contained layer within the semiconductor layer to thereby form an ohmic contact.
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公开(公告)号：GB2566664A8
公开(公告)日：2019-03-27
申请号：GB201901265
申请日：2017-06-13
Applicant: IBM
Inventor： HARIKLIA DELIGIANNI , EUGENE O'SULLIVAN , NAIGANG WANG , BRUCE DORIS
IPC: H01F17/00 , H01L23/522
Abstract: A magnetic laminating structure includes alternating layers of a magnetic material (112) and a multilayered insulating material, wherein the multilayered insulating material is intermediate adjacent magnetic material layers and comprises a first insulating layer (114A) abutting at least on additional insulating layer (114B), and wherein the first insulating layer (114A) and the at least one additional insulating layer (114B) comprise different dielectric materials and/or are formed by a different deposition process.
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公开(公告)号：GB2566664A
公开(公告)日：2019-03-20
申请号：GB201901265
申请日：2017-06-13
Applicant: IBM
Inventor： HARIKLIA DELIGIANNI , EUGENE O'SULLIVAN , NAIGANG WANG , BRUCE DORIS
IPC: H01F17/00 , H01L23/522
Abstract: A magnetic laminating structure includes alternating layers of a magnetic material (112) and a multilayered insulating material, wherein the multilayered insulating material is intermediate adjacent magnetic material layers and comprises a first insulating layer (114A) abutting at least on additional insulating layer (114B), and wherein the first insulating layer (114A) and the at least one additional insulating layer (114B) comprise different dielectric materials and/or are formed by a different deposition process.
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公开(公告)号：GB2575748A
公开(公告)日：2020-01-22
申请号：GB201915102
申请日：2018-03-20
Applicant: IBM
Inventor： SUFI ZAFAR , EUGENE O'SULLIVAN , BRUCE DORIS
IPC: A61B5/053
Abstract: A sensor includes a sensing circuit (116, 126) and a probe (112, 122) communicatively coupled to the sensing circuit (116, 126). The probe (112, 122) includes a three-dimensional (3D) sensing surface coated with a recognition element and configured to, based at least in part on the 3D sensing surface interacting with a predetermined material, generate a first measurement. In some embodiments, the 3D sensing surface is shaped as a pyramid, a cone, or a cylinder to increase the sensing surface area over a two- dimensional (2D) sensing surface. In some embodiments, the 3D sensing facilitates penetration of the 3D sensing surface through the wall of the biological cell (142A).
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Patent Agency Ranking
公开(公告)号：GB2566664B
公开(公告)日：2020-03-11
申请号：GB201901265
申请日：2017-06-13
Applicant: IBM
Inventor： HARIKLIA DELIGIANNI , EUGENE O'SULLIVAN , NAIGANG WANG , BRUCE DORIS
IPC: H01F17/00 , H01L23/522
Abstract: A magnetic laminating structure and process includes alternating layers of a magnetic material and a multilayered insulating material, wherein the multilayered insulating material is intermediate adjacent magnetic material layers and comprises a first insulating layer abutting at least one additional insulating layer, wherein the first insulating layer and the at least one additional insulating layer comprise different dielectric materials and/or are formed by a different deposition process, and wherein the layers of the magnetic material have a cumulative thickness greater than 1 micron.
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公开(公告)号：GB2536814A
公开(公告)日：2016-09-28
申请号：GB201604426
申请日：2016-03-16
Applicant: IBM
Inventor： HARIKLIA DELIGIANNI , NAIGANG WANG , LUBOMYR ROMANKIW , WILLIAM JOSEPH GALLAGHER , ANDREW JOHN KELLOCK , EUGENE O'SULLIVAN
Abstract: An on-chip (on die) magnetic structure manufactured on a semiconductor (Si, GaAs, SiC) substrate 110, comprising (in sequence from substrate) an adhesive layer 120 upon which is deposited a Ni, Co, Pd or Cu seed layer 130 which has been further activated by immersion in a palladium Pd rich solution, to form a thin Pd nanoparticle over-layer 510. The cobalt-tungsten-phosphorus layer 610 is deposited by electroless plating on the palladium rich seed layer 510, 130 to form a high electrical resistivity Pd/CoWP magnetic layer 610/510 (620). The layers may be conventionally defined by photolithography. The magnetic material 620 comprises cobalt Co in a range 80 - 90 atomic percent (at. %) based on the total number of atoms of the magnetic material, tungsten (W) in a range from 4 to 9 atomic percent, and phosphorous (P) in a range from 7 to 15 atomic percent, (and more preferably 9 to 11 at%), the material further comprising palladium Pd dispersed throughout the magnetic material. The Palladium comprising Cobalt-Tungsten-Phosphorus (Pd + CoWP or Pd/CoWP) magnetic material 620 is preferably amorphous. The on chip magnetic structure resistivity is in excess of 100 µΩ.cm. The on chip magnetic structure may be a magnetic yoke, slab, inductor or transformer. The magnetic seed layer may be at least 40nm thick, the Pd-CoWP magnetic layer 620 having thickness 200nm to 1200nm (1.2µm). Applications for the magnetic structure may include miniature power converters.
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公开(公告)号：GB2600899B
公开(公告)日：2022-11-02
申请号：GB202202503
申请日：2020-07-31
Applicant: IBM
Inventor： POUYA HASHEMI , BRUCE DORIS , EUGENE O'SULLIVAN , MICHAEL F LOFARO
Abstract: A memory structure is provided that avoids high resistance due to the galvanic effect. The high resistance is reduced and/or eliminated by providing a T-shaped bottom electrode structure of uniform construction (i.e., a single piece). The T-shaped bottom electrode structure includes a narrow base portion and a wider shelf portion. The shelf portion of the T-shaped bottom electrode structure has a planar topmost surface in which a MTJ pillar forms an interface with.
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公开(公告)号：GB2575748B
公开(公告)日：2022-07-13
申请号：GB201915102
申请日：2018-03-20
Applicant: IBM
Inventor： SUFI ZAFAR , EUGENE O'SULLIVAN , BRUCE DORIS
IPC: G01N27/403 , A61B5/053 , C12Q1/6837
Abstract: Embodiments of the invention include a method of using a sensor. The method includes accessing a sample and exposing the sample to the sensor. The sensor includes a sensing circuit having with a field effect transistor (FET) having a gate structure. A cavity is formed in a fill material that is over the gate structure. A probe of the sensor is within a portion of the cavity. An upper region of the probe is above a top surface of the fill material, and a lower region of the probe is below the top surface of the fill material. The probe structure includes a 3D sensing surface structure, and a liner is formed on the 3D sensing surface and configured to function as a recognition element. A portion of the liner is on the lower region of the probe and positioned between sidewalls of the cavity and the 3D sensing surface.
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公开(公告)号：GB2600899A
公开(公告)日：2022-05-11
申请号：GB202202503
申请日：2020-07-31
Applicant: IBM
Inventor： POUYA HASHEMI , BRUCE DORIS , EUGENE O'SULLIVAN , MICHAEL F LOFARO
Abstract: A memory structure is provided that avoids high resistance due to the galvanic effect. The high resistance is reduced and/or eliminated by providing a T-shaped bottom electrode structure of uniform construction (i.e., a single piece). The T-shaped bottom electrode structure includes a narrow base portion and a wider shelf portion. The shelf portion of the T-shaped bottom electrode structure has a planar topmost surface in which a MTJ pillar forms an interface with.
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