公开(公告)号：EP2047506A4

公开(公告)日：2012-04-25

申请号：EP07783916

申请日：2007-05-18

Applicant: IBM

Inventor： STANDAERT THEODORUS E ,  DAVIS PEGEEN M ,  FITZSIMMONS JOHN A ,  GRECO STEPHEN E ,  KO TZE-MAN ,  LUSTIG NAFTALI E ,  NICHOLSON LEE M ,  SANKARAN SUJATHA

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1721334A4

公开(公告)日：2010-04-07

申请号：EP05711281

申请日：2005-01-06

Applicant: IBM

Inventor： EDELSTEIN DANIEL ,  NICHOLSON LEE M

IPC: H01L23/34 ,  H01L23/053 ,  H01L23/12 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/3135 ,  H01L23/3121 ,  H01L23/3178 ,  H01L23/3185 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2224/29099 ,  H01L2924/00

公开(公告)号：JP2005217420A

公开(公告)日：2005-08-11

申请号：JP2005021358

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDELSTEIN DANIEL C ,  COLBURN MATTHEW E ,  COONEY EDWARD C III ,  DALTON TIMOTHY J ,  FITZSIMMONS JOHN A ,  GAMBINO JEFFREY P ,  HUANG ELBERT E ,  LANE MICHAEL W ,  MCGAHAY VINCENT J ,  NICHOLSON LEE M ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  SANKARAN SUJATHA ,  SHAW THOMAS M ,  SIMON ANDREW H ,  STAMPER ANTHONY K

IPC: H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC classification number: B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device of high strength that lowers an effective dielectric constant k eff , maintains an inter-level vertical capacity in an interconnection at a low level and a manufacturing method of the same. SOLUTION: The method of manufacturing the device comprises a step for providing a structure having an insulating layer 120 of at least one interconnection 130 and a step for forming a sublithographic template mask 150 on the insulating layer. A sublithographic feature 135a is formed in the vicinity of at least one intereconnection by performing etching on the insulating layer through the sublithographic template mask using a selective etching step. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种降低有效介电常数k eff 的高强度半导体器件，将互连中的级间垂直容量保持在低水平，并且制造方法 一样的。 解决方案：制造该器件的方法包括提供具有至少一个互连130的绝缘层120和在绝缘层上形成亚光刻模板掩模150的步骤的结构的步骤。 通过使用选择性蚀刻步骤，通过通过亚光刻模板掩模对绝缘层进行蚀刻，在至少一个相互连接附近形成亚光刻部件135a。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005051214A

公开(公告)日：2005-02-24

申请号：JP2004187691

申请日：2004-06-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NICHOLSON LEE M ,  TSENG WEI-TSU ,  TYBERG CHRISTY

IPC: H01L21/283 ,  H01L21/304 ,  H01L21/31 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5329 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/7688 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an electrical interconnection structure on a substrate including a first low-k dielectric layer, a spin-on low-k CMP protective layer covalently bonded to the first low-k dielectric layer, and a CVD-bonded hard mask/CMP polishing stop layer. SOLUTION: An electrical via 13 and a wire 11 can be formed in a first low-k dielectric layer 3. A spin-on low-k CMP protective layer 5 prevents a damage which may occur on the low-k dielectric 3 due to an uneven CMP process from the center to an edge or in an area varied in metal density. By adjusting the thickness of the low-k CMP protective layer 5, it is possible to respond to a large change in the CMP process without seriously affecting the effective permittivity of a structure 9. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了在包括第一低k电介质层，共价键合到第一低k电介质层的旋涂低k CMP保护层的基板上提供电互连结构和CVD 键合硬掩模/ CMP抛光停止层。 解决方案：电通孔13和导线11可以形成在第一低k电介质层3中。自旋低k CMP保护层5防止在低k电介质3上可能发生的损坏 由于从中心到边缘或在金属密度不同的区域中的不均匀CMP工艺。 通过调整低k CMP保护层5的厚度，可以对CMP工艺的大变化作出反应，而不会严重影响结构9的有效介电常数。（C）2005，JPO＆NCIPI

公开(公告)号：WO2008016740A3

公开(公告)日：2008-06-26

申请号：PCT/US2007069219

申请日：2007-05-18

Applicant: IBM ,  STANDAERT THEODORUS E ,  DAVIS PEGEEN M ,  FITZSIMMONS JOHN A ,  GRECO STEPHEN E ,  KO TZE-MAN ,  LUSTIG NAFTALI E ,  NICHOLSON LEE M ,  SANKARAN SUJATHA

Inventor： STANDAERT THEODORUS E ,  DAVIS PEGEEN M ,  FITZSIMMONS JOHN A ,  GRECO STEPHEN E ,  KO TZE-MAN ,  LUSTIG NAFTALI E ,  NICHOLSON LEE M ,  SANKARAN SUJATHA

IPC: H01L21/4763

CPC classification number: H01L21/76808 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.

Abstract translation: 一种在层间电介质（ILD）材料中形成互连结构的方法，所述方法包括以下步骤：在所述ILD材料中形成一个或多个通孔开口; 形成覆盖所述一个或多个通孔开口中的至少一个的第一衬里; 在由所述第一衬里覆盖的所述一个或多个通孔开口中的至少一个的顶部上创建一个或多个沟槽开口; 以及形成覆盖沟槽开口和第一衬里的至少一部分的第二衬里。 还提供了由该方法形成的互连结构。

公开(公告)号：WO2005067598A3

公开(公告)日：2006-11-23

申请号：PCT/US2005000289

申请日：2005-01-06

Applicant: IBM ,  EDELSTEIN DANIEL ,  NICHOLSON LEE M

Inventor： EDELSTEIN DANIEL ,  NICHOLSON LEE M

IPC: H01L23/34 ,  H01L23/053 ,  H01L23/12 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/3135 ,  H01L23/3121 ,  H01L23/3178 ,  H01L23/3185 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2224/29099 ,  H01L2924/00

Abstract: A structure for a chip (11) or chip package is disclosed, with final passivation (17) and terminal metallurgy which are mechanically decoupled but electrically coupled to the multilayer on-chip interconnects. This decoupling allows the chip to survive packaging stresses in the final passivation region, with strain relief from the decoupling region and compliant leads (14) therein, so that on-chip interconnect levels do not feel these external packaging or other stresses. This structure is particularly preferred for on-chip interconnects consisting of Cu and low-k dielectric, the latter having inferior mechanical properties relative to Si0 2 . The decoupled region extends over all chips on the wafer. It may also extend into the edgeseal or dicing channel region so as to allow chip dicing and retention of this mechanical decoupling all around every chip on the wafer.

Abstract translation: 公开了一种用于芯片（11）或芯片封装的结构，其中最终钝化（17）和终端冶金机械地去耦合但电耦合到多层片上互连。 该去耦允许芯片在最终钝化区域中经受包装应力，其中去耦区域和柔性引线（14）的应变消除，使得片上互连电平不会感受到这些外部封装或其它应力。 这种结构对于由Cu和低k电介质组成的片上互连是特别优选的，后者相对于Si 2 O 2具有较差的机械性能。 去耦区延伸在晶片上的所有芯片上。 它还可以延伸到edgeseal或切割通道区域，以便允许在晶片上的每个芯片周围的这种机械去耦的芯片切割和保持。