公开(公告)号：EP1639655A4

公开(公告)日：2008-03-05

申请号：EP04777407

申请日：2004-07-01

Applicant: IBM

Inventor： HORTON ROBERT S ,  MILTON DAVID W ,  OGILVIE CLARENCE R ,  SCHANELY PAUL M ,  VENTRONE SEBASTIAN T

IPC: G06F13/42 ,  H01L31/107 ,  H04L25/14

CPC classification number: G06F13/4247 ,  H04L25/14

Abstract: The invention transmits data on an integrated circuit chip by first propagating a first data portion along a first segment (120) of a segmented data line (120-122) and then propagating the first data portion along a second segment (121) of the segmented data line and simultaneously propagating a second data portion along the first segment of the segmented data line. The invention breaks a single data transmission into such different data portions and later reassembles the different data portions back into the single data transmission after all of the different data portions have been individually transmitted along all portions of the segmented data line.

公开(公告)号：EP1673867A4

公开(公告)日：2007-07-18

申请号：EP04795023

申请日：2004-10-13

Applicant: IBM

Inventor： GOODNOW KENNETH J ,  OGILVIE CLARENCE R ,  REYNOLDS CHRISTOPHER B ,  SMITH JACK R ,  VENTRONE SEBASTIAN T

IPC: H03K19/173 ,  G06F15/78 ,  H03K19/177

CPC classification number: H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

Abstract: A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

公开(公告)号：WO2007139536A3

公开(公告)日：2009-05-07

申请号：PCT/US2006020462

申请日：2006-05-21

Applicant: IBM ,  COURCHESNE ADAM J ,  GOODNOW KENNETH J ,  HARDING W RIYON ,  MILTON DAVID W ,  NORMAN JASON M ,  OGILVIE CLARENCE R ,  ROTTELLA JASON E ,  SCHANELY PAUL M ,  VENTRONE SEBASTIAN T

Inventor： COURCHESNE ADAM J ,  GOODNOW KENNETH J ,  HARDING W RIYON ,  MILTON DAVID W ,  NORMAN JASON M ,  OGILVIE CLARENCE R ,  ROTTELLA JASON E ,  SCHANELY PAUL M ,  VENTRONE SEBASTIAN T

IPC: H04L12/50

CPC classification number: H04L49/15 ,  H04L49/109 ,  H04L49/252

Abstract: A method and apparatus for providing communication between various cores (1-5) located in an integrated circuit. The method and apparatus uses Hubs/Routers (6-10) to facilitate and manage communication of data from /between the cores (1-5) according to a specified methodology.

Abstract translation: 一种用于在位于集成电路中的各种核心（1-5）之间提供通信的方法和装置。 该方法和装置使用集线器/路由器（6-10）根据指定的方法来促进和管理/内核（1-5）之间的数据通信。

公开(公告)号：WO2005006453A8

公开(公告)日：2007-03-15

申请号：PCT/US2004021244

申请日：2004-07-01

Applicant: IBM ,  HORTON ROBERT S ,  MILTON DAVID W ,  OGILVIE CLARENCE R ,  SCHANELY PAUL M ,  VENTRONE SEBASTIAN T

Inventor： HORTON ROBERT S ,  MILTON DAVID W ,  OGILVIE CLARENCE R ,  SCHANELY PAUL M ,  VENTRONE SEBASTIAN T

IPC: H01L31/107 ,  G06F13/42 ,  H04L25/14

CPC classification number: G06F13/4247 ,  H04L25/14

Abstract: The invention transmits data on an integrated circuit chip by first propagating a first data portion along a first segment (120) of a segmented data line (120-122) and then propagating the first data portion along a second segment (121) of the segmented data line and simultaneously propagating a second data portion along the first segment of the segmented data line. The invention breaks a single data transmission into such different data portions and later reassembles the different data portions back into the single data transmission after all of the different data portions have been individually transmitted along all portions of the segmented data line.

Abstract translation: 本发明通过首先沿着分段数据线（120-122）的第一段（120）传播第一数据部分，然后沿着分段数据线（120-122）的第二段（121）传播第一数据部分，在集成电路芯片上传输数据 数据线并沿着分段数据线的第一段同时传播第二数据部分。 本发明将单个数据传输划分成这样的不同数据部分，并且在所有不同的数据部分已经沿着分段数据线的所有部分单独发送之后，将不同的数据部分重新组合成单​​个数据传输。

公开(公告)号：WO2005038592A2

公开(公告)日：2005-04-28

申请号：PCT/US2004033803

申请日：2004-10-13

Applicant: IBM ,  GOODNOW KENNETH J ,  OGILVIE CLARENCE R ,  REYNOLDS CHRISTOPHER B ,  SMITH JACK R ,  VENTRONE SEBASTIAN T

Inventor： GOODNOW KENNETH J ,  OGILVIE CLARENCE R ,  REYNOLDS CHRISTOPHER B ,  SMITH JACK R ,  VENTRONE SEBASTIAN T

IPC: G06F15/78 ,  H03K19/177 ,  G06F

CPC classification number: H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

Abstract: A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

Abstract translation: 包括RLA（108）和用于在循环基础上重编程RLA的编程器（112）的可重配置逻辑阵列（RLA）系统（104）。 需要比RLA中包含的逻辑量​​更大的函数（F）被分割成多个功能块（FB1，FB2，FB3）。 编程器包含将RLA分割成位于两个存储区域SR1，SR2之间的功能区域FR的软件（144）。 程序员然后用函数的功能块顺序地编程功能区，使得功能块在存储区之间交替方向上处理。 当编程人员用下一个功能块重新配置功能区域并重新配置用于接收下一个功能块的输出的存储区域时，从当前功能块传送到下一个功能块的数据被保存在另一个存储区域中。

公开(公告)号：DE68903292D1

公开(公告)日：1992-12-03

申请号：DE68903292

申请日：1989-03-02

Applicant: IBM

Inventor： OAKLAND STEVEN F ,  OGILVIE CLARENCE R

IPC: G01R31/317 ,  G01R31/28 ,  H03K17/00 ,  H03K17/693

Abstract: A logic circuit is provided which includes a multiplexer (10) having a plurality of parallelly arranged channels (D0-D3), each channel including a switching device (TN0-TN3) having a control element and responsive to a first control signal, a plurality of signal terminals, a common terminal (OUT), each of the channels being connected between a respective one of the plurality of signal terminals and the common terminal, and a termination circuit (14) which includes a series circuit having a plurality of switching devices (TP0-TP3), each having a control element and being responsive to a second control signal. The control elements of each of the plurality of switching devices (TP0-TP3) of the series circuit are coupled to a respective one of the control elements of the switching devices (TN0-TN3) of the channels (D0-D3) so that when one of the switching devices of the series circuit is turned on, the respective one of the switching devices of the channels is turned off, and vice versa.

公开(公告)号：CA1271560A

公开(公告)日：1990-07-10

申请号：CA548401

申请日：1987-10-01

Applicant: IBM

Inventor： BECHADE ROLAND A ,  HOFFMAN WILLIAM K ,  OGILVIE CLARENCE R

IPC: G06F7/53 ,  G06F7/508 ,  G06F7/52

Abstract: DIGITAL BINARY ARRAY MULTIPLIERS Digital binary multipliers are provided which include first and second inverting full adders, each having first, second and third input terminals and first and second output terminals, the first output terminal of the first adder being connected to the first input terminal of the second adder with the first, second and third input terminals and the first and second output terminals of the second adder having a relationship with respect to the input and output terminals of the first adder such that corresponding input and output terminals have opposite signal polarities or complementary terminals, i.e., when one of these input or output terminals of the first adder has a true polarity signal, its corresponding input or output terminal of the second adder has a complemented polarity signal. BU-9-85-027

公开(公告)号：DE68903292T2

公开(公告)日：1993-04-22

申请号：DE68903292

申请日：1989-03-02

Applicant: IBM

Inventor： OAKLAND STEVEN F ,  OGILVIE CLARENCE R

IPC: G01R31/317 ,  G01R31/28 ,  H03K17/00 ,  H03K17/693

Abstract: A logic circuit is provided which includes a multiplexer (10) having a plurality of parallelly arranged channels (D0-D3), each channel including a switching device (TN0-TN3) having a control element and responsive to a first control signal, a plurality of signal terminals, a common terminal (OUT), each of the channels being connected between a respective one of the plurality of signal terminals and the common terminal, and a termination circuit (14) which includes a series circuit having a plurality of switching devices (TP0-TP3), each having a control element and being responsive to a second control signal. The control elements of each of the plurality of switching devices (TP0-TP3) of the series circuit are coupled to a respective one of the control elements of the switching devices (TN0-TN3) of the channels (D0-D3) so that when one of the switching devices of the series circuit is turned on, the respective one of the switching devices of the channels is turned off, and vice versa.