公开(公告)号：DE68903292D1

公开(公告)日：1992-12-03

申请号：DE68903292

申请日：1989-03-02

Applicant: IBM

Inventor： OAKLAND STEVEN F ,  OGILVIE CLARENCE R

IPC: G01R31/317 ,  G01R31/28 ,  H03K17/00 ,  H03K17/693

Abstract: A logic circuit is provided which includes a multiplexer (10) having a plurality of parallelly arranged channels (D0-D3), each channel including a switching device (TN0-TN3) having a control element and responsive to a first control signal, a plurality of signal terminals, a common terminal (OUT), each of the channels being connected between a respective one of the plurality of signal terminals and the common terminal, and a termination circuit (14) which includes a series circuit having a plurality of switching devices (TP0-TP3), each having a control element and being responsive to a second control signal. The control elements of each of the plurality of switching devices (TP0-TP3) of the series circuit are coupled to a respective one of the control elements of the switching devices (TN0-TN3) of the channels (D0-D3) so that when one of the switching devices of the series circuit is turned on, the respective one of the switching devices of the channels is turned off, and vice versa.

公开(公告)号：AU2003213195A1

公开(公告)日：2004-09-17

申请号：AU2003213195

申请日：2003-02-20

Applicant: IBM

Inventor： ZUCHOWSKI PAUL S ,  OAKLAND STEVEN F ,  GATTIKER ANNE ,  NIGH PHIL ,  PASTEL LEAH ,  HORN JODY VAN

IPC: G01R31/3185 ,  H01L23/544 ,  H01L23/58 ,  H02J9/00

Abstract: A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands, each powered by a respective island source voltage, and a testing circuit, coupled to the voltage islands, and powered by a global source voltage that is always on during test, wherein each island source voltage may be independently controlled during test.

公开(公告)号：GB2501853A

公开(公告)日：2013-11-06

申请号：GB201314831

申请日：2012-01-16

Applicant: IBM

Inventor： LACROIX LUKE D ,  LAMOREY MARK C H ,  OAKLAND STEVEN F ,  PATEL JANAK G ,  PFARR KERRY P ,  SLOTA PETER ,  STONE DAVID B

IPC: G01R31/02 ,  G01R31/28

Abstract: Detection circuits, methods of use and manufacture and design structures are provided herein. The structure (25) includes at least one signal line (30) traversing one or more metal layers (20) of an integrated circuit. Circuitry (35) is coupled to the at least one signal line, which is structured to receive a signal with a known signal value (VDD) from the at least one signal line or a signal from a different potential (GND) and, based on which signal is received; determine whether there is a structural defect in the integrated circuit.

公开(公告)号：DE112012000256T5

公开(公告)日：2013-08-29

申请号：DE112012000256

申请日：2012-01-16

Applicant: IBM

Inventor： LACROIX LUKE D ,  OAKLAND STEVEN F ,  PFARR KERRY ,  PATEL JANAK G ,  LAMOREY MARK C H ,  SLOTA PETER ,  STONE DAVID

IPC: G01R31/00

Abstract: Hierin werden Erkennungsschaltungen, Anwendungs- und Herstellungsverfahren und Entwurfsstrukturen bereitgestellt. Die Struktur (25) weist mindestens eine Signalleitung (30) auf, die eine oder mehrere Metallschicht(en) (20) einer integrierten Schaltung durchquert. Mit der mindestens einen Signalleitung ist eine Schaltung (35) verbunden, die strukturiert ist, um ein Signal mit einem bekannten Signalwert (VDD) von der mindestens einen Signalleitung oder ein Signal von einem anderen Potential (GND) zu empfangen und abhängig davon, welches Signal empfangen wird, zu bestimmen, ob ein struktureller Fehler in der integrierten Schaltung vorliegt.

公开(公告)号：DE68903292T2

公开(公告)日：1993-04-22

申请号：DE68903292

申请日：1989-03-02

Applicant: IBM

Inventor： OAKLAND STEVEN F ,  OGILVIE CLARENCE R

IPC: G01R31/317 ,  G01R31/28 ,  H03K17/00 ,  H03K17/693

Abstract: A logic circuit is provided which includes a multiplexer (10) having a plurality of parallelly arranged channels (D0-D3), each channel including a switching device (TN0-TN3) having a control element and responsive to a first control signal, a plurality of signal terminals, a common terminal (OUT), each of the channels being connected between a respective one of the plurality of signal terminals and the common terminal, and a termination circuit (14) which includes a series circuit having a plurality of switching devices (TP0-TP3), each having a control element and being responsive to a second control signal. The control elements of each of the plurality of switching devices (TP0-TP3) of the series circuit are coupled to a respective one of the control elements of the switching devices (TN0-TN3) of the channels (D0-D3) so that when one of the switching devices of the series circuit is turned on, the respective one of the switching devices of the channels is turned off, and vice versa.