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    MICROWORD CONTROL SYSTEM UTILIZING MULTIPLEXED PROGRAMMABLE LOGIC ARRAYS
    1.
    发明专利
    MICROWORD CONTROL SYSTEM UTILIZING MULTIPLEXED PROGRAMMABLE LOGIC ARRAYS 未知

    公开(公告)号：DE3364296D1

    公开(公告)日：1986-08-07

    申请号：DE3364296

    申请日：1983-02-01

    Applicant: IBM

    Inventor： KRAFT WAYNE RICHARD ,  MOORE VICTOR STEWARD ,  PARKER TONY EDWIN ,  RHODES JOSEPH CULLEN ,  STAHL WILLIAM LEONARD ,  VENESKI GERARD ANTHONY

    IPC: G06F9/22 ,  G06F9/28

    Abstract: A microword control system is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword control system includes a plurality of programmable logic array mechanisms responsive to the processor instruction to be executed for individually producing different ones of the microwords needed to execute such instruction. This microword control system also includes microword-responsive control circuitry for controlling the operation of the data processor. This microword control system further includes multiplexing circuitry for supplying microwords from different ones of the programmable logic array mechanisms to the control circuitry during different time intervals.

    SIGNAL LINE PRECHARGING TRISTATE DRIVE CIRCUIT
    3.
    发明专利
    SIGNAL LINE PRECHARGING TRISTATE DRIVE CIRCUIT 未知

    公开(公告)号：DE3476616D1

    公开(公告)日：1989-03-09

    申请号：DE3476616

    申请日：1984-08-01

    Applicant: IBM

    Inventor： KRAFT WAYNE RICHARD ,  MOORE VICTOR STEWART ,  STAHL WILLIAM LEONARD ,  THOMA NANDOR GYORGY

    IPC: H03K19/0175 ,  H03K5/02 ,  H03K19/094 ,  H03K19/20 ,  G11C8/00

    Abstract: The signal line precharging tristate driver circuit quickly and automatically precharges its off-chip signal line to the desired level just before it switches to its tristate or high impedance output condition. This is accomplished by providing precharge circuitry (10) coupled to the driver circuit (4 through 9) and responsive to the tristate control signal for overriding the normal input data signal and causing the driver circuit to commence charging the signal line. There is further provided tristate circuitry (20, 30, 31, 34, 35, 37, 38, 39) coupled to the driver circuit and responsive to its output voltage level for switching the driver circuit to the high impedance output condition when its output voltage and, hence, the signal line voltage reaches a desired predetermined value.

    CIRCUIT FOR SPEEDING UP TRANSFERS OF CHARGES IN PROGRAMMABLE LOGIC ARRAY STRUCTURES
    5.
    发明专利
    CIRCUIT FOR SPEEDING UP TRANSFERS OF CHARGES IN PROGRAMMABLE LOGIC ARRAY STRUCTURES 未知

    公开(公告)号：DE3373964D1

    公开(公告)日：1987-11-05

    申请号：DE3373964

    申请日：1983-06-16

    Applicant: IBM

    Inventor： CASES MOISES ,  KRAFT WAYNE RICHARD ,  STAHL WILLIAM LEONARD ,  THOMA NANDOR GYORGY

    IPC: H03K19/096 ,  H03K19/177 ,  H03K19/094 ,  H03K5/15

    Abstract: Circuit for speeding up transfers of charges in a Programmed Logic Array structure, formed by FET devices (3) in serially chained charge transfer circuits, comprising a level shifting circuit (21) integrated into bit partitioning stages of the structure, for reducing voltage swings in the outputs of those stages and thereby reducing spurious couplings at the inputs of the AND array chains (24) as well as decreasing operational delays of the latter stage, discrete capacitance, (29), added at the output end of the OR array stage (10) for sustaining and reinforcing charge conditions accumulated in that stage prior to readout of that stage, and a source of time related clocking functions (Cp1-Cv3) coupled to stages of the modified structures, with timing relationship selected so as to reduce operational delays of the entire structure while improving its integrity of operation.

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