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公开(公告)号:DE3369753D1
公开(公告)日:1987-03-12
申请号:DE3369753
申请日:1983-01-28
Applicant: IBM
Inventor: RHODES JOSEPH CULLEN , MOORE VICTOR STUART , KRAFT WAYNE RICHARD , BARRS JOHN WILLIAM
Abstract: The microword generation mechanism includes a first cycle programmable logic array (40) responsive to the processor instruction to be executed for providing the first microword needed in the execution of such instruction, a second cycle programmable logic array (41) responsive to the processor instruction to be executed for providing the second microword needed in the execution of such instruction, and at least one additional programmable logic array (42, 43) responsive to the processor instruction to be executed for providing the remainder of the microwords needed to perform the effective address calculations for the operands of the instruction, to fetch the operands from the main storage unit and to execute the operations called for by the instruction.
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公开(公告)号:DE3069518D1
公开(公告)日:1984-11-29
申请号:DE3069518
申请日:1980-11-18
Applicant: IBM
Inventor: MOORE VICTOR , KRAFT WAYNE , RHODES JOSEPH CULLEN , STHAL WILLIAM LEONARD
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公开(公告)号:DE3364296D1
公开(公告)日:1986-08-07
申请号:DE3364296
申请日:1983-02-01
Applicant: IBM
Inventor: KRAFT WAYNE RICHARD , MOORE VICTOR STEWARD , PARKER TONY EDWIN , RHODES JOSEPH CULLEN , STAHL WILLIAM LEONARD , VENESKI GERARD ANTHONY
Abstract: A microword control system is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword control system includes a plurality of programmable logic array mechanisms responsive to the processor instruction to be executed for individually producing different ones of the microwords needed to execute such instruction. This microword control system also includes microword-responsive control circuitry for controlling the operation of the data processor. This microword control system further includes multiplexing circuitry for supplying microwords from different ones of the programmable logic array mechanisms to the control circuitry during different time intervals.
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公开(公告)号:DE3265105D1
公开(公告)日:1985-09-05
申请号:DE3265105
申请日:1982-11-23
Applicant: IBM
Inventor: MOORE VICTOR STEWART , KRAFT WAYNE RICHARD , RHODES JOSEPH CULLEN
IPC: H03K19/177 , G06F9/22 , H03M7/00
Abstract: A multi-bit operation code (22) is decoded into a single product term in the AND array (20) of a programmable logic array. That single product term is then processed through a clock (45) driven sequencer (32) to generate a plurality of sequential product term signals. These sequential product terms are decoded by the OR array (30) of the programmable logic array to generate a plurality of sequential time states (58) corresponding to the decoded operation code (22).
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