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    Finned memory cell and its fabricating method
    4.
    发明专利
    Finned memory cell and its fabricating method 审中-公开
    精细记忆细胞及其制作方法

    公开(公告)号：JP2003318286A

    公开(公告)日：2003-11-07

    申请号：JP2003107565

    申请日：2003-04-11

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： FRIED DAVID M ,  EDWARD J NOWAKU ,  RAINEY BETH ANN

    IPC: H01L21/8242 ,  H01L21/336 ,  H01L21/84 ,  H01L27/02 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  H01L31/0328

    CPC classification number: H01L27/10838 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10888 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

    Abstract: PROBLEM TO BE SOLVED: To provide a memory cell, and its fabricating method, in which cell density can be increased without increasing the fabrication cost or the complicacy excessively.
    SOLUTION: A fin arrangement forming a memory cell is provided. More concretely, an access transistor is provided by forming a finned field effect transistor (FET) and a storage capacitor is provided by forming a finned capacitor. When the memory cell is formed using a finned FET and a finned capacitor, memory cell density can be increased significantly as compared with the conventional planar capacitor arrangement. Furthermore, a memory cell can be fabricated with significantly lower process cost and complicacy than those of the conventional deep trench capacitor arrangement.
    COPYRIGHT: (C)2004,JPO

    Abstract translation: 要解决的问题：提供一种其中可以增加细胞密度而不增加制造成本或过度复杂的存储单元及其制造方法。 提供形成存储单元的翅片布置。 更具体地，通过形成翅片场效应晶体管（FET）提供存取晶体管，并且通过形成鳍式电容器来提供存储电容器。 当使用有鳍FET和鳍状电容器形成存储单元时，与常规平面电容器布置相比，可以显着提高存储单元密度。 此外，与传统的深沟槽电容器布置相比，可以以显着更低的工艺成本和复杂性制造存储器单元。 版权所有（C）2004，JPO

    MULTI-HEIGHT FINFETS
    5.
    发明申请
    MULTI-HEIGHT FINFETS 审中-公开
    多高熔点金属

    公开(公告)号：WO2004100290A3

    公开(公告)日：2005-02-24

    申请号：PCT/US2004002647

    申请日：2004-01-30

    Applicant: IBM ,  RAINEY BETH ANN ,  NOWAK EDWARD J ,  ALLER INGO DR ,  KEINERT JOACHIM ,  LUDWIG THOMAS

    Inventor： RAINEY BETH ANN ,  NOWAK EDWARD J ,  ALLER INGO DR ,  KEINERT JOACHIM ,  LUDWIG THOMAS

    IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/772

    CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66795

    Abstract: The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2/3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.

    Abstract translation: 本发明提供一种具有第一鳍片和第二鳍片的FinFET器件。 每个散热片具有从沟道区延伸的沟道区和源极和漏极区。 翅片具有不同的高度。 本发明具有邻近散热片定位的栅极导体。 栅极导体垂直于翅片延伸并与第一鳍片和第二鳍片中的每一个的沟道区域交叉。 翅片彼此平行。 第一翅片的高度与第二翅片的高度的比率为1/2/3的比例。 该比率用于调整晶体管的性能并确定晶体管的总通道宽度。

    7.
    发明专利
    未知

    公开(公告)号：DE602004015592D1

    公开(公告)日：2008-09-18

    申请号：DE602004015592

    申请日：2004-01-30

    Applicant: IBM

    Inventor： RAINEY BETH ANN ,  NOWAK EDWARD J ,  ALLER INGO DR ,  KEINERT JOACHIM ,  LUDWIG THOMAS

    IPC: H01L21/336 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

    Abstract: The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2/3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.

    Fin fet devices from bulk semiconductor and method for forming
    8.
    发明专利
    Fin fet devices from bulk semiconductor and method for forming 未知

    公开(公告)号：AU2003237320A8

    公开(公告)日：2003-12-19

    申请号：AU2003237320

    申请日：2003-06-03

    Applicant: IBM

    Inventor： SADANA DEVENDRA K ,  NOWAK EDWARD J ,  RAINEY BETH ANN ,  FRIED DAVID M

    IPC: H01L27/088 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8232

    Abstract: The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET devices from bulk semiconductor wafers while providing improved wafer to wafer device uniformity. Specifically, the method facilitates the formation of finFET devices from bulk semiconductor wafers with improved fin height control. Additionally, the method provides the ability to form finFETs from bulk semiconductor while providing isolation between fins and between the source and drain region of individual finFETs. Finally, the method can also provide for the optimization of fin width. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

    FIN FET DEVICES FROM BULK SEMICONDUCTOR AND METHOD FOR FORMING
    9.
    发明专利
    FIN FET DEVICES FROM BULK SEMICONDUCTOR AND METHOD FOR FORMING 未知

    公开(公告)号：AU2003237320A1

    公开(公告)日：2003-12-19

    申请号：AU2003237320

    申请日：2003-06-03

    Applicant: IBM

    Inventor： FRIED DAVID M ,  NOWAK EDWARD J ,  RAINEY BETH ANN ,  SADANA DEVENDRA K

    IPC: H01L27/088 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/786

    Abstract: The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET devices from bulk semiconductor wafers while providing improved wafer to wafer device uniformity. Specifically, the method facilitates the formation of finFET devices from bulk semiconductor wafers with improved fin height control. Additionally, the method provides the ability to form finFETs from bulk semiconductor while providing isolation between fins and between the source and drain region of individual finFETs. Finally, the method can also provide for the optimization of fin width. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

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