公开(公告)号：EP1620891A4

公开(公告)日：2007-03-28

申请号：EP04707026

申请日：2004-01-30

Applicant: IBM

Inventor： RAINEY BETH ANN ,  NOWAK EDWARD J ,  ALLER INGO DR ,  KEINERT JOACHIM ,  LUDWIG THOMAS

IPC: H01L21/84 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66795

Abstract: The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2/3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.

公开(公告)号：JP2000068277A

公开(公告)日：2000-03-03

申请号：JP21494799

申请日：1999-07-29

Applicant: IBM

Inventor： ENGLISH GEORGE ,  KEINERT JOACHIM ,  RETTIG OLIVER DR

IPC: H01L21/3205 ,  H01L21/304 ,  H01L21/82 ,  H01L23/48

Abstract: PROBLEM TO BE SOLVED: To effectively design a semiconductor integrated circuit or an electronic package without considerably increasing complexity of data or reducing wire resistance, by dividing a wide metallic area into metallic stripes. SOLUTION: A physical designing step includes the step of dividing a wide metallic area 4 into metallic stripes 2. The wide metallic area 4 is preferably separated into the stripes 2 which belong to a single wire segment, and vias 6 are inserted only into overlapping parts between metallic layers. An upper metallic layer is provided with an electronic structural element, preferably a C4 pad area 8 for mounting a chip. A blockage is set so as to prevent metallic segments from overlapping the C4 pad area 8. A long power line is divided from an edge to another edge, is formed into stripes on a part on which the C4 pad area 8 is not disposed, and is divided on a part on which the C4 pad area 8 is disposed.

公开(公告)号：JP2005197685A

公开(公告)日：2005-07-21

申请号：JP2004370239

申请日：2004-12-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ALLER INGO ,  GERNHOEFER VEIT ,  KEINERT JOACHIM ,  LUDWIG THOMAS

IPC: G03F1/08 ,  G06F17/50 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/08 ,  H01L27/088 ,  H01L29/786

CPC classification number: H01L29/785 ,  G06F17/5068 ,  H01L21/823821 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To provide a reliable method and a device which enable design-keeping transition from an existing non-fin design structure to a functionally identical structure based on a technology of a double-gate fin-base field-effect transistor FinFET in a metal-oxide semiconductor MOS, a device of a complementary metal-oxide semiconductor CMOS, and designing chips of the semiconductors. SOLUTION: The corresponding cell structure "C" 512 contains an arrangement of a cell structure "A" and a cell structure "B" that include no previously generated fins. Consideration is made on arrangement combinations of a cell structure "A" and a cell structure "B" generated in this design hierarchy to other cell structures. A fin generation tool decides not to arrange the fins in the cell structure "A" and cell structure "B" in this hierarchy. The fin generation is delegated to the hierarchy, thus revealing a combined fin shape 560 without steps as indicated by a circle. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种可靠的方法和装置，其使得能够基于双栅极鳍基场场效应技术将设计保持从现有非鳍设计结构转换到功能相同的结构 金属氧化物半导体MOS中的晶体管FinFET，互补金属氧化物半导体CMOS的器件，以及半导体的芯片的设计。 解决方案：相应的单元结构“C”512包含单元结构“A”和单元结构“B”的布置，其不包括先前生成的散热片。 考虑在该设计层级中生成的单元结构“A”和单元结构“B”与其它单元结构的组合。 翅片生成工具决定不将散热片排列在该层次结构中的单元结构“A”和单元结构“B”。 翅片一代被委托给层级，从而显示出一个组合的翅片形状560，没有由圆圈指示的步骤。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：DE3371960D1

公开(公告)日：1987-07-09

申请号：DE3371960

申请日：1983-08-17

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： BROSCH RUDOLF DR ING ,  KEINERT JOACHIM ,  KLINK ERICH DIPL ING ,  WERNICKE FRIEDRICH C DIPL ING

IPC: H03K3/286 ,  H03K3/288 ,  H03K5/02 ,  H03K5/151

Abstract: A phase splitter with latch comprises a true complement generator in the form of a current switch (T1, T2, T3, R3) which supplies two complementary output signals in response to an input signal (VIN). The outputs of this true complement generator are in each case connected to an associated emitter follower (T4, T5). The two emitter followers (T4, T5) have identical emitter resistors (R6, R7) which simultaneously serve as collector load resistors of two cross-coupled transistors (T6, T7) also comprise identical but higher emitter resistors (R13, R14) than the emitter followers (T6, T7). The emitters of the cross-coupled transistors (T6, T7) are each connected to one of the two inputs of an output stage (T8, T9, T11) consisting of a current switch. This current switch is connected to operating voltage (VEE) through a clock-controlled transitor (T11). Upon actuation of the output stage, i.e., when transistor (T11) is on, the active emitter resistance of one of the cross-coupled transistors (T6, T7) is pulled below the value of the emitter resistors (R6, R7) of the emitter followers (T4, T5), thus causing the latch circuit to be latched as a function of the input signal.

公开(公告)号：WO2004100290A3

公开(公告)日：2005-02-24

申请号：PCT/US2004002647

申请日：2004-01-30

Applicant: IBM ,  RAINEY BETH ANN ,  NOWAK EDWARD J ,  ALLER INGO DR ,  KEINERT JOACHIM ,  LUDWIG THOMAS

Inventor： RAINEY BETH ANN ,  NOWAK EDWARD J ,  ALLER INGO DR ,  KEINERT JOACHIM ,  LUDWIG THOMAS

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/772

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66795

Abstract: The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2/3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.

Abstract translation: 本发明提供一种具有第一鳍片和第二鳍片的FinFET器件。 每个散热片具有从沟道区延伸的沟道区和源极和漏极区。 翅片具有不同的高度。 本发明具有邻近散热片定位的栅极导体。 栅极导体垂直于翅片延伸并与第一鳍片和第二鳍片中的每一个的沟道区域交叉。 翅片彼此平行。 第一翅片的高度与第二翅片的高度的比率为1/2/3的比例。 该比率用于调整晶体管的性能并确定晶体管的总通道宽度。

公开(公告)号：AT403937T

公开(公告)日：2008-08-15

申请号：AT04707026

申请日：2004-01-30

Applicant: IBM

Inventor： RAINEY BETH ,  NOWAK EDWARD ,  ALLER INGO ,  KEINERT JOACHIM ,  LUDWIG THOMAS

IPC: H01L21/84 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

Abstract: The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2/3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.

公开(公告)号：BR8404041A

公开(公告)日：1985-09-03

申请号：BR8404041

申请日：1984-08-13

Applicant: IBM

Inventor： BROSCH RUDOLF ,  KEINERT JOACHIM ,  KLINK ERICH ,  WERNICKE FRIEDRICH C

IPC: H03K3/286 ,  H03K3/288 ,  H03K5/02 ,  H03K5/151 ,  H03K19/00

Abstract: A phase splitter with latch comprises a true complement generator in the form of a current switch (T1, T2, T3, R3) which supplies two complementary output signals in response to an input signal (VIN). The outputs of this true complement generator are in each case connected to an associated emitter follower (T4, T5). The two emitter followers (T4, T5) have identical emitter resistors (R6, R7) which simultaneously serve as collector load resistors of two cross-coupled transistors (T6, T7) also comprise identical but higher emitter resistors (R13, R14) than the emitter followers (T6, T7). The emitters of the cross-coupled transistors (T6, T7) are each connected to one of the two inputs of an output stage (T8, T9, T11) consisting of a current switch. This current switch is connected to operating voltage (VEE) through a clock-controlled transitor (T11). Upon actuation of the output stage, i.e., when transistor (T11) is on, the active emitter resistance of one of the cross-coupled transistors (T6, T7) is pulled below the value of the emitter resistors (R6, R7) of the emitter followers (T4, T5), thus causing the latch circuit to be latched as a function of the input signal.

公开(公告)号：DE602004015592D1

公开(公告)日：2008-09-18

申请号：DE602004015592

申请日：2004-01-30

Applicant: IBM

Inventor： RAINEY BETH ANN ,  NOWAK EDWARD J ,  ALLER INGO DR ,  KEINERT JOACHIM ,  LUDWIG THOMAS

IPC: H01L21/336 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

Abstract: The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2/3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.