公开(公告)号：EP1745515A4

公开(公告)日：2009-04-01

申请号：EP04822011

申请日：2004-04-22

Applicant: IBM

Inventor： FREEMAN GREGORY G ,  RIEH JAE-SUNG ,  SHERIDAN DAVID C ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D ,  VOLDMAN STEVEN H

IPC: H01L29/00 ,  H01L21/331 ,  H01L21/332 ,  H01L29/08 ,  H01L29/737 ,  H01L29/74 ,  H01L29/861 ,  H01L29/872 ,  H01L29/93

CPC classification number: H01L29/66363 ,  H01L29/0821 ,  H01L29/0834 ,  H01L29/66242 ,  H01L29/7378 ,  H01L29/74 ,  H01L29/861 ,  H01L29/872 ,  H01L29/93

Abstract: Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.

公开(公告)号：JP2004304190A

公开(公告)日：2004-10-28

申请号：JP2004090598

申请日：2004-03-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KHATER MARWAN H ,  RIEH JAE-SUNG ,  STRICKER ANDREAS D ,  GREGORY G FREEMAN ,  SCHONENBERG KATHRYN T

IPC: H01L29/70 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L29/0649 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a bipolar transistor structure, capable of reducing the parasitic capacitance.
SOLUTION: A method for forming a vertical bipolar transistor, comprising the steps of forming a bipolar transistor on silicon semiconductor substrate 11 which has an upper surface; forming STI regions 14 which are made of dielectric materials and have an inside edge portion and an upper surface, respectively; forming a doped collector region C between a pair of STI regions; also forming a counter doped intrinsic base region IB between the pair of STI regions, wherein there is each margin between the intrinsic base region and the pair of STI regions, and the intrinsic base region has edges; forming a doped-emitter region on the intrinsic base region apart from the edges; and forming shallow separated extension regions IE made of dielectric materials in the above margins, and placing them in parallel with the edges of the intrinsic base region; and forming an outer base region which covers the shallow separated extension regions partially, and further extends to the intrinsic base region, thereby physically and electrically contacting with the intrinsic base region.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004221582A

公开(公告)日：2004-08-05

申请号：JP2004003465

申请日：2004-01-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN HUAJIE ,  SCHONENBERG KATHRYN T ,  GREGORY G FREEMAN ,  STRICKER ANDREAS D ,  RIEH JAE-SUNG

IPC: H01L21/321 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L21/32105 ,  Y10S438/911

Abstract: PROBLEM TO BE SOLVED: To provide a self-aligning oxide mask formed by utilizing the difference in oxidation speed between different materials.
SOLUTION: The self-aligning oxide mask is formed on a CVD growth base NPN base layer including a single crystal Si52 (Si/SiGe) in an active area and a poly-crystal Si51 (Si/SiGe). The self-aligning mask is fabricated by utilizing the fact that the poly-crystal Si (Si/SiGe) oxidizes faster than the single crystal Si (Si/SiGe). By using the thermal oxidation method, a thick oxide layer is formed on the poly-crystal Si (Si/SiGe) and a thin oxide layer is formed on the single crystal Si (Si/SiGe), thereby the oxide films are formed on both the poly-crystal Si (Si/SiGe) and the single crystal Si (Si/SiGe), and by the control of etching of the oxide, the thin oxide layer on the single crystal Si (Si/SiGe) is removed while the self-alignment oxide mask layer is left on the poly-crystal Si (Si/SiGe).
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：AT518249T

公开(公告)日：2011-08-15

申请号：AT04822011

申请日：2004-04-22

Applicant: IBM

Inventor： FREEMAN GREGORY ,  RIEH JAE-SUNG ,  SHERIDAN DAVID ,  ST ONGE STEPHEN ,  STRICKER ANDREAS ,  VOLDMAN STEVEN

IPC: H01L29/732 ,  H01L21/331 ,  H01L21/332 ,  H01L29/00 ,  H01L29/08 ,  H01L29/737 ,  H01L29/74 ,  H01L29/861 ,  H01L29/872 ,  H01L29/93

Abstract: Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.