公开(公告)号：EP1658639A4

公开(公告)日：2009-09-30

申请号：EP04777467

申请日：2004-07-01

Applicant: IBM

Inventor： KHATER MARWAN H ,  DUNN JAMES S ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  LIU QIZHI ,  PAGETTE FRANCOIS ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D

IPC: H01L29/732 ,  H01L21/331 ,  H01L29/10 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

公开(公告)号：EP1745515A4

公开(公告)日：2009-04-01

申请号：EP04822011

申请日：2004-04-22

Applicant: IBM

Inventor： FREEMAN GREGORY G ,  RIEH JAE-SUNG ,  SHERIDAN DAVID C ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D ,  VOLDMAN STEVEN H

IPC: H01L29/00 ,  H01L21/331 ,  H01L21/332 ,  H01L29/08 ,  H01L29/737 ,  H01L29/74 ,  H01L29/861 ,  H01L29/872 ,  H01L29/93

CPC classification number: H01L29/66363 ,  H01L29/0821 ,  H01L29/0834 ,  H01L29/66242 ,  H01L29/7378 ,  H01L29/74 ,  H01L29/861 ,  H01L29/872 ,  H01L29/93

Abstract: Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.

公开(公告)号：JP2004304190A

公开(公告)日：2004-10-28

申请号：JP2004090598

申请日：2004-03-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KHATER MARWAN H ,  RIEH JAE-SUNG ,  STRICKER ANDREAS D ,  GREGORY G FREEMAN ,  SCHONENBERG KATHRYN T

IPC: H01L29/70 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L29/0649 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a bipolar transistor structure, capable of reducing the parasitic capacitance.
SOLUTION: A method for forming a vertical bipolar transistor, comprising the steps of forming a bipolar transistor on silicon semiconductor substrate 11 which has an upper surface; forming STI regions 14 which are made of dielectric materials and have an inside edge portion and an upper surface, respectively; forming a doped collector region C between a pair of STI regions; also forming a counter doped intrinsic base region IB between the pair of STI regions, wherein there is each margin between the intrinsic base region and the pair of STI regions, and the intrinsic base region has edges; forming a doped-emitter region on the intrinsic base region apart from the edges; and forming shallow separated extension regions IE made of dielectric materials in the above margins, and placing them in parallel with the edges of the intrinsic base region; and forming an outer base region which covers the shallow separated extension regions partially, and further extends to the intrinsic base region, thereby physically and electrically contacting with the intrinsic base region.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：WO2005024900A3

公开(公告)日：2005-06-09

申请号：PCT/US2004021345

申请日：2004-07-01

Applicant: IBM ,  KHATER MARWAN H ,  DUNN JAMES S ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  LIU QIZHI ,  PAGETTE FRANCOIS ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D

Inventor： KHATER MARWAN H ,  DUNN JAMES S ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  LIU QIZHI ,  PAGETTE FRANCOIS ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737 ,  H01L23/62

CPC classification number: H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter (106) is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer (102) of polysilicon or silicon on an intrinsic base (108). A dielectric landing pad (128) is then formed by lithography on the first extrinsic base layer (102). Next, a second extrinsic base layer (104) of polysilicon or silicon is formed on top of the dielectric landing pad (128) to finalize the raised extrinsic base total thickness. An emitter (106) opening is formed using lithography and RIE, where the second extrinsic base layer (104) is etched stopping on the dielectric landing pad (128). The degree of self-alignment between the emitter (106) and the raised extrinsic base is achieved by selecting the first extrinsic base layer (102) thickness, the dielectric landing pad (128) width, and the spacer width.

Abstract translation: 公开了一种具有凸起的非本征基极和在本征基极和发射极（106）之间的可选自对准的双极晶体管。 制造方法可以包括在内在基极（108）上形成多晶硅或硅的第一非本征基极层（102）的预定厚度。 然后通过光刻在第一非本征基极层（102）上形成电介质着色焊盘（128）。 接下来，在电介质着色焊盘（128）的顶部上形成多晶硅或硅的第二非本征基极层（104），以最终确定凸出的非本征基本总厚度。 使用光刻和RIE形成发射器（106）开口，其中第二外部基极层（104）被蚀刻停止在电介质着色焊盘（128）上。 通过选择第一非本征基极层（102）的厚度，电介质着陆焊盘（128）的宽度和间隔物宽度来实现发射极（106）和凸起的外在基极之间的自对准程度。

公开(公告)号：JP2005260239A

公开(公告)日：2005-09-22

申请号：JP2005066770

申请日：2005-03-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GEISS PETER J ,  MARWAN H KHATER ,  LIU QIZHI ,  RANDY W MANN ,  PURTELL ROBERT J ,  BETHANN RAINEY ,  JAE-SUNG RIEH ,  STRICKER ANDREAS D

IPC: H01L21/28 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a hetero-junction bipolar transistor having a raised base of which the base resistance is decreased by forming silicide extending to an emitter region in a self-aligning manner on a raised base.
SOLUTION: This silicide formation is incorporated in a BiCMOS process flow after forming a raised and extrinsic base. The bipolar transistor has the raised and extrinsic base, and the hetero-junction bipolar transistor has silicide positioned on the raised and extrinsic base. The silicide on the extrinsic base extends to an emitter in a self-aligning manner. The emitter is isolated from the silicide by a spacer.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种通过在自升高的基极上以自对准的方式形成延伸到发射极区域的硅化物来提供具有升高的基极的异质结双极晶体管的方法，其中基极电阻降低。 解决方案：该硅化物形成在形成凸起和外在基体之后并入BiCMOS工艺流程中。 双极晶体管具有凸起和非本征基极，并且异质结双极晶体管具有位于升高和外部基极上的硅化物。 外在基极上的硅化物以自对准方式延伸到发射极。 发射极通过间隔物与硅化物隔离。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004221582A

公开(公告)日：2004-08-05

申请号：JP2004003465

申请日：2004-01-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN HUAJIE ,  SCHONENBERG KATHRYN T ,  GREGORY G FREEMAN ,  STRICKER ANDREAS D ,  RIEH JAE-SUNG

IPC: H01L21/321 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L21/32105 ,  Y10S438/911

Abstract: PROBLEM TO BE SOLVED: To provide a self-aligning oxide mask formed by utilizing the difference in oxidation speed between different materials.
SOLUTION: The self-aligning oxide mask is formed on a CVD growth base NPN base layer including a single crystal Si52 (Si/SiGe) in an active area and a poly-crystal Si51 (Si/SiGe). The self-aligning mask is fabricated by utilizing the fact that the poly-crystal Si (Si/SiGe) oxidizes faster than the single crystal Si (Si/SiGe). By using the thermal oxidation method, a thick oxide layer is formed on the poly-crystal Si (Si/SiGe) and a thin oxide layer is formed on the single crystal Si (Si/SiGe), thereby the oxide films are formed on both the poly-crystal Si (Si/SiGe) and the single crystal Si (Si/SiGe), and by the control of etching of the oxide, the thin oxide layer on the single crystal Si (Si/SiGe) is removed while the self-alignment oxide mask layer is left on the poly-crystal Si (Si/SiGe).
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：DE112011101373B4

公开(公告)日：2015-12-31

申请号：DE112011101373

申请日：2011-05-17

Applicant: IBM

Inventor： JOSEPH ALVIN J ,  STRICKER ANDREAS D ,  HARAME DAVID L ,  DAHLSTROM MATTIAS E ,  GRAY PETER B ,  HERRIN RUSSELL T ,  CAMILLO-CASTILLO RENATA

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737

Abstract: Verfahren zur Bildung eines Transistors, aufweisend: Bilden einer intrinsischen Basisschicht (120) auf einer Oberseite eines Halbleitersubstrats (101); Bilden einer dielektrischen Schicht (130) auf der intrinsischen Basisschicht; Bilden einer extrinsischen Basisschicht (140) auf der dielektrischen Schicht; Bilden mindestens einer zweiten dielektrischen (302) Schicht auf der extrinsischen Basisschicht; Bilden einer Öffnung (315), die durch die mindestens eine zweite dielektrische Schicht zu der extrinsischen Basisschicht verläuft, wobei die Öffnung eine erste vertikale Seitenwand (306) aufweist; Bilden einer Seitenwand-Abstandsopferschicht (307) auf der ersten vertikalen Seitenwand; Bilden einer dielektrischen Opferschicht (309) auf einer freiliegenden Fläche der extrinsischen Basisschicht benachbart zu der Seitenwand-Abstandsopferschicht; selektives Entfernen der Seitenwand-Abstandsopferschicht; Bilden, zwischen der ersten vertikalen Seitenwand und der dielektrischen Opferschicht, eines Grabens (170), der durch die extrinsische Basisschicht und die erste dielektrische Schicht zu der intrinsischen Basisschicht verläuft, derart, dass der Graben an einen Umfang der Öffnung angepasst ist und eine zweite vertikale Seitenwand (175) aufweist, die direkt unter der ersten vertikalen Seitenwand mit dieser ausgerichtet ist; Bilden eines leitenden Streifens (150) innerhalb des Grabens benachbart zu der Seitenwand derart, dass der leitende Streifen die intrinsische Basisschicht mit der extrinsischen Basisschicht elektrisch verbindet; nach dem Bilden des leitenden Streifens, Bilden eines ersten Abschnitts (161) einer dielektrischen Abstandsschicht auf der ersten vertikalen Seitenwand (306), und der mindestens eine Oberseite des leitenden Streifens bedeckt; ...

公开(公告)号：GB2494358B

公开(公告)日：2014-04-16

申请号：GB201300063

申请日：2011-05-17

Applicant: IBM

Inventor： CAMILLO-CASTILLO RENATA ,  DAHLSTROM MATTIAS E ,  GRAY PETER B ,  HARAME DAVID L ,  HERRIN RUSSELL T ,  JOSEPH ALVIN ,  STRICKER ANDREAS D

IPC: H01L29/06 ,  H01L21/331 ,  H01L29/10 ,  H01L29/66 ,  H01L29/732 ,  H01L29/737

Abstract: Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method allows for self-aligning of the emitter to base regions and incorporates the use of a sacrificial dielectric layer, which must be thick enough to withstand etch and cleaning processes and still remain intact to function as an etch stop layer when the conductive strap is subsequently formed. A chemically enhanced high pressure, low temperature oxidation (HIPOX) process can be used to form such a sacrificial dielectric layer.

公开(公告)号：DE112011101373T5

公开(公告)日：2013-03-14

申请号：DE112011101373

申请日：2011-05-17

Applicant: IBM

Inventor： JOSEPH ALVIN J ,  STRICKER ANDREAS D ,  HARAME DAVID L ,  CAMILIO-CASTILIO RENATA ,  DAHLSTROM MATTIAS E ,  GRAY PETER B ,  HERRIN RUSSELL T

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737

Abstract: Ausführungsformen einer verbesserten Transistorstruktur (100) (z. B. einer Bipolartransistor(BT)-Struktur oder Heteroübergang-Bipolartransistor(HBT)-Struktur) und ein Verfahren zur Bildung der Transistorstruktur (100) werden offenbart. Die Ausführungsformen der Struktur können eine dielektrische Schicht (130), die zwischen einer intrinsischen Basisschicht (120) und einer erhabenen extrinsischen Basisschicht (140) angeordnet ist, um die Kollektor-Basis-Kapazität Ccb zu reduzieren, einen seitenwanddefinierten leitenden Streifen (150) für eine Verbindungszone von der intrinsischen Basisschicht (120) zur extrinsischen Basisschicht (140), um den Basis-Widerstand Rb zu reduzieren, und eine dielektrische Abstandsschicht (160) zwischen der extrinsischen Basisschicht (140) und einer Emitterschicht (180) aufweisen, um die Basis-Emitter-Kapazität Cbe zu reduzieren. Die Ausführungsformen des Verfahrens erlauben die Selbstjustierung des Emitters zu Basiszonen und erlauben zudem die selektive Anpassung der Geometrien verschiedener Merkmale (z. B. der Dicke der dielektrischen Schicht (130), der Breite des leitenden Streifens (150), der Breite der dielektrischen Abstandsschicht (160) und der Breite der Emitterschicht (180)), um die Transistorleistungsfähigkeit zu optimieren.

公开(公告)号：GB2494358A

公开(公告)日：2013-03-06

申请号：GB201300063

申请日：2011-05-17

Applicant: IBM

Inventor： CAMILLO-CASTILLO RENATA ,  DAHLSTROM MATTIAS E ,  GRAY PETER B ,  HARAME DAVID L ,  HERRIN RUSSELL T ,  JOSEPH ALVIN ,  STRICKER ANDREAS D

IPC: H01L29/06 ,  H01L21/331 ,  H01L29/10 ,  H01L29/66 ,  H01L29/732 ,  H01L29/737

Abstract: Disclosed are embodiments of an improved transistor structure (100) (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure (100). The structure embodiments can incorporate a dielectric layer (130) sandwiched between an intrinsic base layer (120) and a raised extrinsic base layer (140) to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap (150) for an intrinsic base layer (120) to extrinsic base layer (140) link-up region to reduce base resistance Rb and a dielectric spacer (160) between the extrinsic base layer (140) and an emitter layer (180) to reduce base- emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer (130), the width of the conductive strap (150), the width of the dielectric spacer (160) and the width of the emitter layer (180)) to be selectively adjusted in order to optimize transistor performance.