公开(公告)号：JP2001326470A

公开(公告)日：2001-11-22

申请号：JP2001087939

申请日：2001-03-26

Applicant: IBM

Inventor： DONS FRANCIS J JR ,  FARQUHAR DONALD S ,  FOUST ELIZABETH ,  ROBERT M JAPPU ,  JONES GERALD W ,  JOHN S KURIIJU ,  ROBERT D SEBESUTA ,  DAVID B STONE ,  JAMES R WILCOCKS

IPC: H05K1/02 ,  H01L23/12 ,  H01L23/14 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide an electronic package and a method of manufacturing the electronic package. SOLUTION: A package 10 is provided with a semiconductor chip 12 and a multilayer interconnection structure 18 having an allyl surface layer. The semiconductor chip 12 has a plurality of contact members 16 on one surface, and is connected with the inside of the multilayer interconnection structure 18 by using a plurality of solder connecting members 20. The multilayer interconnection structure 18 is constituted so as to electrically and interconnect circuits of a board 100 by using a plurality of other solder connecting members 47 and has a heat conduction layer 22 composed of material having a selected thickness and coefficient of thermal expansion with which solder connecting obstruction between a plurality of first conducting members and the semiconductor chip is prevented totally. The electronic package 10 includes dielectric material having effective tensile stress for ensuring sufficient compliancy with the multilayer interconnection structure 18 during operation. The allyl surface layer has characteristic capable of enduring thermal stress which is generated during heat cycle operation of the electronic package 10.

公开(公告)号：JP2001308480A

公开(公告)日：2001-11-02

申请号：JP2001054795

申请日：2001-02-28

Applicant: IBM

Inventor： ADVOCATE JR GERALD G ,  DONS FRANCIS J JR ,  MATIENZO LUIS J ,  KASCHAK RONALD A ,  JOHN S KURESUGE ,  VAN HART DANIEL C

IPC: C23C18/18 ,  C25D7/00 ,  H01L21/60 ,  H01L23/498 ,  H01L23/522 ,  H05K1/11 ,  H05K3/00 ,  H05K3/02 ,  H05K3/06 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide an electronic structure having a conductive plating layer where adhesion of plating is enhanced. SOLUTION: A substrate having a metal sheet in a dielectric layer is used. The metal sheet contains a metal, e.g. copper. An opening, e.g. a blind via, is made in the substrate by laser drilling passing through a part of the dielectric layer and the metal sheet. Surface (blind surface) beneath the opening includes a metal protrusion formed by laser drilling and the metal protrusion is integrated with the blind surface. The metal protrusion contains the metal of the metal sheet and at least one component from the dielectric layer. Subsequently, the metal protrusion is etched to form a metal interlock structure integral with a part of the blind surface. A conductive metal is stuck into the opening including the metal interlock structure by plating.