公开(公告)号：WO2012064912A2

公开(公告)日：2012-05-18

申请号：PCT/US2011060084

申请日：2011-11-10

Applicant: IBM ,  JOHNSON JEFFREY B ,  NARASIMHA SHREESH ,  NAYFEH HASAN M ,  ONTALUS VIOREL C ,  ROBINSON ROBERT R

Inventor： JOHNSON JEFFREY B ,  NARASIMHA SHREESH ,  NAYFEH HASAN M ,  ONTALUS VIOREL C ,  ROBINSON ROBERT R

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7824 ,  H01L21/76237 ,  H01L21/84 ,  H01L27/1203

Abstract: A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer (105; Fig. 5) on a buried oxide (BOX) layer (115) of a silicon-on-insulator substrate (100); a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer (160, 165, and 170), a doped region (155) in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer (160), doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer (165), doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.

Abstract translation: 一种结构，一种FET，一种制造该结构和制造该FET的方法。 所述结构包括：在绝缘体上硅衬底（100）上的掩埋氧化物（BOX）层（115）上的硅层（105;图5）; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层（160,165和170），所述硅层中的掺杂区域（155）和邻接 BOX层和沟槽的底部，掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层（160）; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层（165）; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。

公开(公告)号：GB2497259B

公开(公告)日：2013-12-11

申请号：GB201306404

申请日：2011-11-10

Applicant: IBM

Inventor： JOHNSON JEFFREY B ,  NARASIMHA SHREESH ,  NAYFEH HASAN M ,  ONTALUS VIOREL C ,  ROBINSON ROBERT R

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12

公开(公告)号：GB2497259A

公开(公告)日：2013-06-05

申请号：GB201306404

申请日：2011-11-10

Applicant: IBM

Inventor： JOHNSON JEFFREY B ,  NARASIMHA SHREESH ,  NAYFEH HASAN M ,  ONTALUS VIOREL C ,  ROBINSON ROBERT R

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12

Abstract: A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer (105; Fig. 5) on a buried oxide (BOX) layer (115) of a silicon-on-insulator substrate (100); a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer (160, 165, and 170), a doped region (155) in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer (160), doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer (165), doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.