公开(公告)号：EP2168163A4

公开(公告)日：2012-08-01

申请号：EP08771894

申请日：2008-06-25

Applicant: IBM

Inventor： ESHUN EBENEZER E ,  JOHNSON JEFFREY B ,  PHELPS RICHARD A ,  RASSEL ROBERT M ,  ZIERAK MICHAEL L

IPC: H01L29/808 ,  H01L21/337 ,  H01L29/36

CPC classification number: H01L29/808 ,  H01L27/0617 ,  H01L27/098 ,  H01L29/36 ,  H01L29/66901

公开(公告)号：EP1979932A4

公开(公告)日：2012-03-14

申请号：EP07710130

申请日：2007-01-15

Applicant: IBM

Inventor： ERTURK METE ,  GROVES ROBERT A ,  JOHNSON JEFFREY B ,  JOSEPH ALVIN J ,  LIU QIZHI ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

IPC: H01L21/77 ,  H01L21/302 ,  H01L21/306 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1839340A4

公开(公告)日：2009-09-09

申请号：EP05855611

申请日：2005-12-22

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  FURKAY STEPHEN S ,  JOHNSON JEFFREY B ,  RASSEL ROBERT M

IPC: H01L21/20 ,  H01L29/93

CPC classification number: H01L29/93

Abstract: A semiconductor structure comprising a hyperabrupt junction varactor with a compensated cathode contact as well as a method of fabricating the same are disclosed. The method includes a single implant mask which is used in forming the subcollector/cathode, collector/well and hyperabrupt junction.

公开(公告)号：JP2005268802A

公开(公告)日：2005-09-29

申请号：JP2005077513

申请日：2005-03-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： STEPHEN S FURKAY ,  HENDRICK HAMANN ,  JOHNSON JEFFREY B ,  LAM CHUNG H ,  HON-SUM P WONG

IPC: G11C13/00 ,  G11C11/56 ,  H01L21/06 ,  H01L21/331 ,  H01L27/10 ,  H01L27/105 ,  H01L27/12 ,  H01L27/24 ,  H01L29/00 ,  H01L29/68 ,  H01L45/00

CPC classification number: H01L29/685 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/1203

Abstract: PROBLEM TO BE SOLVED: To provide a memory structure in which electric characteristics are controlled by indirectly heating a phase change material. SOLUTION: A manufacturing method of a memory device of a phase change material and a phase change memory device prepared by the method thereof are included. Concretely, the phase change memory device contains a semiconductor structure, and the semiconductor structure includes a substrate where a first doped area is contained and a set of second doped areas are disposed at both ends thereof; the phase change material disposed on the first doped area; and a conductor disposed on the phase change material. The semiconductor structure is operated as a bipolar junction transistor when the phase change material is in a first phase, and the semiconductor structure is operated as a MOSFET when the phase change material is in a second phase. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供通过间接加热相变材料来控制电特性的存储结构。 解决方案：包括通过其方法制备的相变材料的存储器件和相变存储器件的制造方法。 具体地说，相变存储器件包含半导体结构，并且半导体结构包括其两端包含第一掺杂区的基片和一组第二掺杂区; 所述相变材料设置在所述第一掺杂区域上; 以及配置在相变材料上的导体。 当相变材料处于第一相位时，半导体结构作为双极结型晶体管工作，当相变材料处于第二相时，半导体结构作为MOSFET工作。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2012064912A2

公开(公告)日：2012-05-18

申请号：PCT/US2011060084

申请日：2011-11-10

Applicant: IBM ,  JOHNSON JEFFREY B ,  NARASIMHA SHREESH ,  NAYFEH HASAN M ,  ONTALUS VIOREL C ,  ROBINSON ROBERT R

Inventor： JOHNSON JEFFREY B ,  NARASIMHA SHREESH ,  NAYFEH HASAN M ,  ONTALUS VIOREL C ,  ROBINSON ROBERT R

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7824 ,  H01L21/76237 ,  H01L21/84 ,  H01L27/1203

Abstract: A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer (105; Fig. 5) on a buried oxide (BOX) layer (115) of a silicon-on-insulator substrate (100); a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer (160, 165, and 170), a doped region (155) in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer (160), doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer (165), doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.

Abstract translation: 一种结构，一种FET，一种制造该结构和制造该FET的方法。 所述结构包括：在绝缘体上硅衬底（100）上的掩埋氧化物（BOX）层（115）上的硅层（105;图5）; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层（160,165和170），所述硅层中的掺杂区域（155）和邻接 BOX层和沟槽的底部，掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层（160）; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层（165）; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。

公开(公告)号：WO2011162977A3

公开(公告)日：2012-03-15

申请号：PCT/US2011039892

申请日：2011-06-10

Applicant: IBM ,  CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET gate stack includes source and drain extension regions (28) located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel (40) is also present between the source and drain extension regions (28) and beneath the at least one gate stack (18). The structure further includes embedded stressor elements (33) located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material (35) having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material (36) located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact (45) located directly on an upper surface of the delta monolayer (37).

Abstract translation: 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底（12）的上表面上的至少一个FET栅叠层（18）。 所述至少一个FET栅极堆叠包括位于所述至少一个FET栅极堆叠中的覆盖区内的所述半导体衬底内的源极和漏极延伸区域（28）。 器件通道（40）也存在于源极和漏极延伸区域（28）之间并且在至少一个栅极堆叠（18）下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且在半导体衬底内的嵌入式应力元件（33）。 每个嵌入式应力元件包括从底部到顶部具有不同于半导体衬底的晶格常数的晶格常数的第一外延掺杂半导体材料（35）的第一层，并且在器件沟道中施加应变， 位于第一层顶部的第二外延掺杂半导体材料（36）的第二层和位于第二层的上表面上的掺杂剂的Δ单层。 该结构还包括直接位于三角单层（37）的上表面上的金属半导体合金接触（45）。

公开(公告)号：JP2002324806A

公开(公告)日：2002-11-08

申请号：JP2002075491

申请日：2002-03-19

Applicant: IBM

Inventor： FREEMAN GREGORY G ,  JAGANNATHAN BASANTH ,  JENG SHWU-JEN ,  JOHNSON JEFFREY B

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/36 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide an element structure and a method for manufacturing the same for suppressing an increase of an unnecessary capacitance in the element as small as possible and for improving a transistor characteristic. SOLUTION: In an integrated bi-polar circuit element, a stepped collector dopant profile reduces a transit time and a parasitic capacitance between an emitter and a collector due to a minimum increase of the parasitic capacitance. A shallow implantation reduces a width of a space charge region between a base and the collector, reduces a resistance, and individually optimizes a breakdown characteristic between the collector and the base. A deep implantation, then, links a buried collector to a sub-collector and provides a low resistance path to the sub-collector. The stepped collector dopant profile only gives the lowest effect against a capacitance the collector and the base outside an intrinsic region of the element. The reason is that the higher concentration dopant is compensated by an exogenous dopant outside the intrinsic region or is buried therein.

公开(公告)号：JP2002313798A

公开(公告)日：2002-10-25

申请号：JP2002052091

申请日：2002-02-27

Applicant: IBM

Inventor： DUNN JAMES S ,  HARAME DAVID L ,  JOHNSON JEFFREY B ,  ROBB A JOHNSON ,  LANZEROTTI LOUIS D ,  ST ONGE STEPHEN A

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide an epitaxial base bipolar transistor which has low base resistance and whose capacitance does not increase. SOLUTION: This epitaxial base bipolar transistor is provided with an epitaxial silicon layer on a single crystal semiconductor substrate 54, a raised emitter 64 on the surface of the semiconductor substrate, a raised extrinsic base 58e on the surface of the semiconductor substrate, an insulator 66 as a spacer between the raised emitter and raised extrinsic base, and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in the semiconductor substrate. The emitter diffusion has an emitter diffusion junction depth, and the raised emitter extends to the surface of the semiconductor substrate and the raised extrinsic base extends to the surface of the semiconductor substrate. A difference of height between the surfaces of the emitter and base is less than 20% of the emitter diffusion junction depth.

公开(公告)号：JPH11251569A

公开(公告)日：1999-09-17

申请号：JP7399

申请日：1999-01-04

Applicant: IBM

Inventor： JOHNSON JEFFREY B ,  WONG HON-SUM P

IPC: H01L27/146

Abstract: PROBLEM TO BE SOLVED: To provide a photodetector having an array of active pixel sensor(APS) elements formed in cells which are separated respectively by Si. SOLUTION: Each cell has an insulation barrier 10 (10C, etc.), around and lies on an insulation layer 12 which lies on a substrate 14. A semiconductor connector 18 for doing the vertical contact of each APS element between a pinned layer 24 and body 20 is formed pref. so as to occupy the region at a part of the insulation barrier adjacent to each cell and may be simple vertical connection 18 for connecting a plurality of APS elements or a long strip for connecting the plurality of APS elements. Moreover the semiconductor connector 18 may extend to reach a lower insulation layer 12 or pierce the insulation layer 12 to reach the substrate 14 to ground and interconnect the body 20 of each APS element and pinning layer 24. There a method of manufacturing photosensitive elements is also included.

公开(公告)号：WO2007084879A3

公开(公告)日：2008-02-21

申请号：PCT/US2007060544

申请日：2007-01-15

Applicant: IBM ,  ERTURK METE ,  GROVES ROBERT A ,  JOHNSON JEFFREY B ,  JOSEPH ALVIN J ,  LIU QIZHI ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

Inventor： ERTURK METE ,  GROVES ROBERT A ,  JOHNSON JEFFREY B ,  JOSEPH ALVIN J ,  LIU QIZHI ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

IPC: H01L21/00 ,  H01L21/302 ,  H01L21/306 ,  H01L21/44 ,  H01L21/77

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation (250) in a substrate (100), the substrate (100) having a frontside and an opposing backside; forming a first dielectric layer (105) on the frontside of the substrate (100); forming a trench (265C) in the first dielectric layer (105), the trench (265C) aligned over and within a perimeter of the dielectric isolation (250) and extending to the dielectric isolation (250); extending the trench (265C) formed in the first dielectric layer (1 05) through the dielectric isolation (250) and into the substrate (1 00)to a depth (Dl ) less than a thickness of the substrate (1 00); filling the trench (265C) and co-planarizing a top surface of the trench (265C) with a top surface of the first dielectric layer (1 05) to form an electrically conductive through via (270C); and thinning the substrate (100) from a backside of the substrate (100) to expose the through via (270C).

Abstract translation: 背面接触结构及其制造方法。 该方法包括：在衬底（100）中形成绝缘隔离（250），所述衬底（100）具有前侧和相对的背面; 在所述基板（100）的前侧形成第一介电层（105）; 在所述第一电介质层（105）中形成沟槽（265C），所述沟槽（265C）在所述电介质隔离（250）的周边内并且在所述绝缘隔离（250）的周边内并且延伸到所述电介质隔离（250）; 将形成在第一电介质层（105）中的沟槽（265C）延伸通过电介质隔离（250）并延伸到衬底（100）中至小于衬底厚度（001）的深度（D1）。 填充沟槽（265C）并且将沟槽（265C）的顶表面与第一介电层（105）的顶表面共平面化以形成导电通孔（270C）; 以及从所述衬底（100）的背面使所述衬底（100）变薄以暴露所述通孔（270C）。