公开(公告)号：KR20070103701A

公开(公告)日：2007-10-24

申请号：KR20070037961

申请日：2007-04-18

Applicant: QIMONDA AG ,  IBM

Inventor： PHILIPP JAN BORIS ,  ROSSNAGEL STEPHEN M

IPC: H01L21/8247 ,  H01L21/324 ,  H01L27/115

CPC classification number: H01L45/148 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1641 ,  H01L21/28185

Abstract: A method for transitioning the state of the phase change material by annealing is provided to prevent a peeling due to a tensile stress by annealing an amorphous phase change material after a deposition to transit the phase change material to a crystalline state. A method for transitioning the state of the phase change material by annealing includes the steps of: providing a previously processed wafer; depositing the phase change material on the previously processed wafer at an amorphous state(100); and annealing a phase change material so as to transit the phase change material from the amorphous state to a crystalline state(102). The step of annealing the phase change material includes an in-situ annealing of the phase change material layer.

Abstract translation: 提供了通过退火来转变相变材料的状态的方法，以防止在沉积之后使非晶相变材料退火以使相变材料转变为结晶状态而由拉伸应力引起的剥离。 通过退火来转变相变材料的状态的方法包括以下步骤：提供预先处理的晶片; 在非晶状态（100）将相变材料沉积在先前处理的晶片上; 以及使所述相变材料退火以使所述相变材料从所述非晶状态转变为结晶状态（102）。 退火相变材料的步骤包括相变材料层的原位退火。

公开(公告)号：EP1756856A4

公开(公告)日：2010-02-17

申请号：EP05755089

申请日：2005-05-31

Applicant: IBM

Inventor： DUNN DERREN N ,  KIM HYUNGJUN ,  ROSSNAGEL STEPHEN M ,  SEO SOON-CHEON

IPC: H01L21/283 ,  H01L21/285 ,  H01L21/4763 ,  H01L21/52 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/28562 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2534710A4

公开(公告)日：2015-05-06

申请号：EP11742594

申请日：2011-01-10

Applicant: IBM

Inventor： CHUNG LAM H ,  ROSSNAGEL STEPHEN M ,  SCHROTT ALEJANDRO G

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1641 ,  H01L45/1683

公开(公告)号：EP2523748A4

公开(公告)日：2017-03-01

申请号：EP11733229

申请日：2011-01-10

Applicant: IBM

Inventor： AFZALI-ARDAKANI ALI ,  ROSSNAGEL STEPHEN M

IPC: B01D71/02 ,  B01D61/02 ,  B01D67/00 ,  C02F1/44 ,  C02F103/08

CPC classification number: B01D67/0065 ,  B01D61/025 ,  B01D67/0088 ,  B01D71/025 ,  B01D2313/90 ,  C02F1/441 ,  C02F2103/08 ,  C02F2305/08 ,  Y02A20/131

Abstract: A filter includes a membrane having a plurality of nanochannels formed therein. Functionalized nanoparticles are deposited through self assembly onto surfaces defining the nanochannels so as to decrease the final diameter of the membrane. Methods for making and using the filter are also provided.

Abstract translation: 过滤器包括其中形成有多个纳米通道的膜。 官能化纳米颗粒通过自组装沉积到限定纳米通道的表面上，以便降低膜的最终直径。 还提供了制造和使用过滤器的方法。

公开(公告)号：JP2010283347A

公开(公告)日：2010-12-16

申请号：JP2010123865

申请日：2010-05-31

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NOGAMI TAKESHI ,  EDELSTEIN DANIEL C ,  ROSSNAGEL STEPHEN M ,  FLAITZ PHILIP LEE ,  DEHAVEN PATRICK WILLIAM ,  YANG CHIH-CHAO

IPC: H01L21/3205 ,  H01L21/28 ,  H01L23/52

CPC classification number: H01L21/2855 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  Y10T428/24917

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of attaining high reliability and a high production yield by eliminating a void generation portion in a liner/copper interface. SOLUTION: The method of forming a diffusion barrier used for manufacturing the semiconductor device includes a step for depositing an iridium-doped tantalum-based barrier layer on a pattern-formed intermediate dielectric (ILD) layer by a physical vapor deposition (PVD) process, and the barrier layer is deposited to form the barrier layer into amorphous structure as a result, at least 60% of an iridium concentration in terms of atomic weight. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过消除衬里/铜界面中的空隙生成部分来制造能够获得高可靠性和高生产率的半导体器件的方法。 解决方案：形成用于制造半导体器件的扩散阻挡层的方法包括通过物理气相沉积（PVD）在形成图案的中间电介质（ILD）层上沉积铱掺杂的钽基阻挡层的步骤 ），并且阻挡层被沉积以形成无定形结构的阻挡层，至少60％的铱浓度以原子量计。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：WO2005122253A3

公开(公告)日：2006-12-14

申请号：PCT/US2005018953

申请日：2005-05-31

Applicant: IBM ,  DUNN DERREN N ,  KIM HYUNGJUN ,  ROSSNAGEL STEPHEN M ,  SEO SOON-CHEON

Inventor： DUNN DERREN N ,  KIM HYUNGJUN ,  ROSSNAGEL STEPHEN M ,  SEO SOON-CHEON

IPC: H01L21/283 ,  H01L21/285 ,  H01L21/4763 ,  H01L21/52 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/28562 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of depositing a tantalum nitride (TaN) diffusion barrier region on low-k materials. The methods include forming a protective layer (104) on the low-k material substrate (102) by performing plasma-enhanced atomic layer deposition (PE-ALD) from tantalum-based precursor and a nitrogen plasma in a chamber. The protective layer (104) has a nitrogen content greater than its tantalum content. A substantially stoichiometric tantalum-nitride layer is then formed by performing PE-ALD from the tantalum-based precursor and a plasma including hydrogen and nitrogen. The invention also includes the tantalum-nitride diffusion barrier region (108) so formed. In one embodiment, the metal precursor includes tantalum penta-chloride (TaC1 5 ). The invention generates a sharp interface between low-k materials and liner materials.

Abstract translation: 在低k材料上沉积氮化钽（TaN）扩散阻挡区域的方法。 所述方法包括通过从钽基前体和室中的氮等离子体进行等离子体增强的原子层沉积（PE-ALD）在低k材料衬底（102）上形成保护层（104）。 保护层（104）的氮含量大于钽的含量。 然后通过从钽基前体和包括氢和氮的等离子体中进行PE-ALD形成基本上化学计量的氮化钽层。 本发明还包括如此形成的氮化钽 - 氮化物扩散阻挡区域（108）。 在一个实施方案中，金属前体包括五氯化钽（TaCl 5 N 5）。 本发明在低k材料和衬垫材料之间产生尖锐的界面。

公开(公告)号：JP2011188851A

公开(公告)日：2011-09-29

申请号：JP2011027025

申请日：2011-02-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： PENG HONGBO ,  STOLOVITSKY GUSTAVO A ,  ROSSNAGEL STEPHEN M ,  POLONSKY STANISLAV ,  LUAN BINQUAN ,  MARTYNA GLENN J

IPC: C12M1/00 ,  C12Q1/68 ,  G01N27/416

CPC classification number: C12Q1/6869 ,  Y10T29/42 ,  C12Q2565/631

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus, a system and a method for controlling a polymer through a nanopore using a piezoelectric material. SOLUTION: There are provided an apparatus, a system, and a method for using a piezoelectric material for controlling a polymer through a nanopore. A reservoir is formed filled with a conductive fluid. A nanopore is formed through a membrane. The membrane comprises an electroconductive layer, a piezoelectric layer, and an insulating layer. The piezoelectric layer is operative to control a size of the nanopore for clamping/releasing a polymer as well as to control the thickness of part of the membrane when a voltage is applied to the piezoelectric layer. Combinations of clamping/releasing the polymer and changing the thickness of part of the membrane can move a polymer through the nanopore at any electrically controlled speed and also stretch or break a polymer in the nanopore. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种使用压电材料通过纳米孔控制聚合物的装置，系统和方法。 解决方案：提供了一种使用压电材料通过纳米孔控制聚合物的装置，系统和方法。 形成填充有导电流体的储存器。 通过膜形成纳米孔。 膜包括导电层，压电层和绝缘层。 压电层用于控制用于夹紧/释放聚合物的纳米孔的尺寸，以及当向压电层施加电压时控制膜的一部分的厚度。 夹持/释放聚合物和改变膜的一部分厚度的组合可以以任何电控速度移动聚合物通过纳米孔，并且还拉伸或破坏纳米孔中的聚合物。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2011007793A

公开(公告)日：2011-01-13

申请号：JP2010143601

申请日：2010-06-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： PENG HONGBO ,  ROSSNAGEL STEPHEN M ,  POLONSKY STANISLAV ,  STOLOVITZKY GUSTAVO ALEJANDRO

IPC: G01N27/414

CPC classification number: H01L51/0558 ,  B82Y10/00 ,  G01N27/4148 ,  G01N33/48721 ,  H01L51/0093 ,  Y10S977/938

Abstract: PROBLEM TO BE SOLVED: To provide a nanofluidic field effect transistor device.SOLUTION: The field effect transistor device includes a reservoir classified by a membrane of three layers, namely, two electrically insulating layers and an electrically conductive gate arranged therebetween. The gate has a polarity different from a surface charge polarity of at least one of the insulating layers. A nanochannel runs through the membrane, connecting both parts of the reservoir. The device further includes an ionic solution filling the reservoir and the nanochannel, a drain electrode and a source electrode, and a voltage applied between the source electrode and the drain electrode and a voltage applied onto the gate turn on an ionic current through the ionic channel, and the voltage on the gate gates the transportation of ions through the ionic channel.

Abstract translation: 要解决的问题：提供一种纳米流体场效应晶体管器件。解决方案：场效应晶体管器件包括由三层膜分隔的容器，即两个电绝缘层和布置在其间的导电栅极。 栅极具有与至少一个绝缘层的表面电荷极性不同的极性。 纳米通道穿过膜，连接储存器的两个部分。 该装置还包括填充储存器和纳米通道的离子溶液，漏电极和源极，以及施加在源电极和漏电极之间的电压，以及施加到栅极上的电压通过离子通道的离子电流 ，栅极上的电压通过离子通道输送离子。

公开(公告)号：JP2007194624A

公开(公告)日：2007-08-02

申请号：JP2006353015

申请日：2006-12-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MALHOTRA SANDRA G ,  DELIGIANNI HARIKLIA ,  VAN DER STRATEN OSCAR ,  SHAO XIAOYAN ,  ROSSNAGEL STEPHEN M ,  TAI TSONG-LIN

IPC: H01L23/52 ,  C23C16/16 ,  C23C16/56 ,  C25D7/12 ,  H01L21/288 ,  H01L21/3205

CPC classification number: H01L21/76843 ,  H01L21/28562 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  Y10S438/952

Abstract: PROBLEM TO BE SOLVED: To provide a process for direct electroplating of copper on a platable layer which is not copper.
SOLUTION: This process for forming an interconnection in a semiconductor structure comprises a step for forming a dielectric layer on a substrate, a step for forming a first barrier layer on the dielectric layer, and a step for forming a second barrier layer on the first barrier layer. The second barrier layer is selected from a group including ruthenium, platinum, palladium, rhodium and iridium. The second barrier layer is formed by a process including a step for manipulating so that bulk concentration of oxygen in the second barrier layer becomes 20 atm.% or less, and a step for forming a conductive layer on the second barrier layer. This process further can include a step for treating the second barrier to decrease the amount of an oxide on the surface of the second barrier layer.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供在不是铜的可镀层上直接电镀铜的方法。 解决方案：用于在半导体结构中形成互连的该工艺包括在衬底上形成电介质层的步骤，在电介质层上形成第一阻挡层的步骤和用于形成第二阻挡层的步骤 第一阻隔层。 第二阻挡层选自包括钌，铂，钯，铑和铱的组。 第二阻挡层通过包括操作步骤的方法形成，使得第二阻挡层中的氧的体积浓度变为20atm％以下，以及在第二阻挡层上形成导电层的步骤。 该方法还可以包括用于处理第二阻挡层以减少第二阻挡层的表面上的氧化物的量的步骤。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006203197A

公开(公告)日：2006-08-03

申请号：JP2006007419

申请日：2006-01-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BRULEY JOHN ,  CARRUTHERS ROY A ,  LINN MARIE GIGNAC ,  HU CHAO-KUN ,  LINIGER ERIC G ,  MALHOTRA SANDRA G ,  ROSSNAGEL STEPHEN M

IPC: H01L21/768

CPC classification number: H01L21/76849 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an improved on-chip Cu interconnection that uses a metal cap having a thickness of 1 to 5 nm.
SOLUTION: There is disclosed a procedure for coating the surface of a Cu Damascene wire with an element, having a thickness of 1 to 5 nm prior to deposition of an interlayer dielectric or dielectric diffusion barrier layer. The coating brings about protection against oxidization, increases the adhesive force between Cu and the dielectric, and makes the boundary surface diffusion of Cu reduced. Further, the thin cap layer increases the electromigration lifetime of Cu and reduces the occurrence of voids induced by stress. The selected element can be directly deposited on Cu embedded in the dielectric in the lower layer, without causing short-circuiting between the Cu wires. These selected elements are selected, based on the negative high reduction potential with respect to oxygen and water, low solubility to Cu, and the compound formation with Cu.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供使用厚度为1至5nm的金属帽的改进的片上Cu互连。 解决方案：公开了在沉积层间电介质或电介质扩散阻挡层之前，用具有1至5nm厚度的元件涂覆Cu镶嵌线的表面的步骤。 该涂层具有防氧化保护作用，增加了Cu与电介质之间的粘合力，使Cu的边界表面扩散减少。 此外，薄盖层增加了Cu的电迁移寿命并且减少了由应力引起的空隙的发生。 所选择的元件可以直接沉积在嵌入下层电介质中的Cu上，而不会导致Cu线之间的短路。 这些选择的元素基于相对于氧和水的负高还原电位，对Cu的低溶解度和与Cu的化合物形成而选择。 版权所有（C）2006，JPO＆NCIPI