公开(公告)号：WO2004055821A3

公开(公告)日：2004-11-04

申请号：PCT/EP0314011

申请日：2003-12-10

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GOGL DIETMAR ,  SCHEUERLEIN ROY EDWIN ,  REOHR WILLIAM ROBERT

IPC: G11C11/16

CPC classification number: G11C11/1693 ,  G11C11/1673 ,  G11C11/1675

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.

Abstract translation: 磁存储器电路包括多个存储器单元和耦合到存储器单元的多个位线，用于选择性地访问一个或多个存储器单元。 存储器电路包括至少一个位线编程电路，可配置为用于产生用于写入至少一个存储器单元的逻辑状态的编程电流的电流源和/或用于返回编程电流的电流吸收器，以及第一组 开关。 至少在存储器单元的读取操作期间禁用第一组开关，并且在存储器单元的写入操作期间选择性地使能第一组开关的至少一部分。 第一组开关中的每个开关被配置为响应于第一控制信号选择性地将至少一个位线编程电路耦合到对应的位线。 存储器电路还包括至少一个读出放大器和第二组开关。 至少在存储器单元的写入操作期间禁用第二组开关，并且在存储器单元的读取操作期间，第二组开关的至少一部分被选择性地使能。 第二组开关中的每个开关被配置为响应于第二控制信号选择性地将至少一个读出放大器耦合到对应的一个位线。

公开(公告)号：AU2003293828A8

公开(公告)日：2004-07-09

申请号：AU2003293828

申请日：2003-12-10

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GOGL DIETMAR ,  SCHEUERLEIN ROY EDWIN ,  REOHR WILLIAM ROBERT

IPC: G11C11/16

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.

公开(公告)号：DE60320301T2

公开(公告)日：2009-06-25

申请号：DE60320301

申请日：2003-12-10

Applicant: IBM ,  QIMONDA AG

Inventor： GOGL DIETMAR ,  SCHEUERLEIN ROY EDWIN ,  REOHR WILLIAM ROBERT

IPC: G11C11/16

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.

公开(公告)号：DE3379129D1

公开(公告)日：1989-03-09

申请号：DE3379129

申请日：1983-11-03

Applicant: IBM

Inventor： KASPRZAK LUCIAN ALEXANDER ,  RYAN CHARLES TIMOTHY ,  SCHEUERLEIN ROY EDWIN

IPC: G11C29/00 ,  G01R31/28 ,  G11C29/48 ,  G11C29/50

Abstract: A random access memory, a method of manufacturing a random access memory, and a method of testing a random access memory in which separate operating voltage terminal pads (35, 36) are provided for the memory cell arrays (11, 12) and peripheral circuits (14, 15) of the memory. By providing separate operating voltage terminal pads (35, 36), different operating voltages can be applied to the arrays (11, 12) of cells and to the peripheral circuits (14,15) during a burn-in procedure. In this manner, the burn-in procedure is greatly accelerated without danger of damage to the peripheral circuits (14, 15) due to exceeding the sustaining voltages of the transistor devices of the peripheral circuits during burn-in.

公开(公告)号：DE3478882D1

公开(公告)日：1989-08-10

申请号：DE3478882

申请日：1984-03-16

Applicant: IBM

Inventor： SCHEUERLEIN ROY EDWIN

IPC: G11C11/405 ,  G11C11/401 ,  G11C11/4097 ,  G11C11/24

公开(公告)号：DE3072030D1

公开(公告)日：1987-10-22

申请号：DE3072030

申请日：1980-12-04

Applicant: IBM

Inventor： SCHEUERLEIN ROY EDWIN

IPC: G11C11/401 ,  G11C5/06 ,  G11C11/403 ,  G11C11/4097 ,  H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  G11C11/24

Abstract: Disclosed is an integrated circuit electronic memory array having a plurality of FET memory cells (T, C) arranged in rows and columns and formed on the same integrated circuit chip with associated support circuits. Each memory cell (T, C) of the array has a capacitive storage region (C), an adjacent channel region, and a gate region (G) for controlling the transfer or binary information through the channel region in and out of the capacitive storage region (C). Each memory cell (T, C) also has a bit line (BL) contact region which is shared with an adjacent memory cell. The word lines (WL) are arranged in rows in a substantially equidistant parallel relationship, each word line passing, in succession, over the storage region (C) of a first one of the memory cells (T, C) and electrically integral with the gate region (G) of a second one of the memory cells (T, C). The column arrangement of memory cells (T, C) is interdigitated such that the memory cells associated with a single bit line (BL) are arranged in first and second parallel lines (A, B) along both the left and right sides of each bit line (B, L). Thus, the bit line (BL) is arranged in a zig-zag configuration alternately contacting memory cells (T, C) arranged along its left and right side.

公开(公告)号：AU537761B2

公开(公告)日：1984-07-12

申请号：AU6410280

申请日：1980-11-05

Applicant: IBM

Inventor： SCHEUERLEIN ROY EDWIN

IPC: G11C11/401 ,  G11C5/06 ,  G11C11/403 ,  G11C11/4097 ,  H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  G11C11/34

Abstract: Disclosed is an integrated circuit electronic memory array having a plurality of FET memory cells (T, C) arranged in rows and columns and formed on the same integrated circuit chip with associated support circuits. Each memory cell (T, C) of the array has a capacitive storage region (C), an adjacent channel region, and a gate region (G) for controlling the transfer or binary information through the channel region in and out of the capacitive storage region (C). Each memory cell (T, C) also has a bit line (BL) contact region which is shared with an adjacent memory cell. The word lines (WL) are arranged in rows in a substantially equidistant parallel relationship, each word line passing, in succession, over the storage region (C) of a first one of the memory cells (T, C) and electrically integral with the gate region (G) of a second one of the memory cells (T, C). The column arrangement of memory cells (T, C) is interdigitated such that the memory cells associated with a single bit line (BL) are arranged in first and second parallel lines (A, B) along both the left and right sides of each bit line (B, L). Thus, the bit line (BL) is arranged in a zig-zag configuration alternately contacting memory cells (T, C) arranged along its left and right side.

公开(公告)号：DE60320301D1

公开(公告)日：2008-05-21

申请号：DE60320301

申请日：2003-12-10

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  SCHEUERLEIN ROY EDWIN ,  REOHR WILLIAM ROBERT

IPC: G11C11/16

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.

公开(公告)号：SG77251A1

公开(公告)日：2000-12-19

申请号：SG1999003219

申请日：1999-07-06

Applicant: IBM

Inventor： SCHEUERLEIN ROY EDWIN

IPC: G11C11/15 ,  H01L27/115 ,  G11C13/00

Abstract: A nonvolatile memory cell includes a substrate, a diode, a first conductive line, a magnetic tunnel junction device, a by-pass conductor and a second conductive line. The diode is formed in the substrate and includes an n-type region and a p-type region. The first conductive line is formed on the substrate and is electrically connected to the n-type region of the diode. The magnetic tunnel junction device is formed on the first conductive line. The by-pass conductor electrically connects the p-type region of the diode to the magnetic tunnel junction device. The second conductive line is formed on and is electrically connected to the magnetic tunnel junction device.

公开(公告)号：DE3686132D1

公开(公告)日：1992-08-27

申请号：DE3686132

申请日：1986-10-07

Applicant: IBM

Inventor： NOBLE JR ,  SCHEUERLEIN ROY EDWIN ,  WALKER WILLIAM WARREN

IPC: H01L21/76 ,  H01L21/033 ,  H01L21/265 ,  H01L21/762 ,  H01L27/10 ,  H01L27/105 ,  H01L21/00

Abstract: A process is provided for making two self-aligned recessed oxide isolation regions (24, 28) of different thicknesses which includes the steps of defining first and second spaced apart regions (16, 18) on the surface of a semiconductor substrate (10), forming a protective layer (20) over the second region (18), forming a first insulating layer (24) of a given thickness within the first region (16) while the second region is protected by the protective layer, removing the protective layer (20) from the second region and forming a second insulating layer (28) thinner than that of the first layer (24) within the second region. Field regions (22, 26) may be ion implanted prior to forming the insulating layers.