公开(公告)号：CA2062135A1

公开(公告)日：1992-11-24

申请号：CA2062135

申请日：1992-03-02

Applicant: IBM

Inventor： MCCAULEY DONALD W ,  SCHMALZ RICHARD J ,  SMITH RONALD M SR ,  STILLMAN SUSAN B

IPC: G06F13/42 ,  G06F12/02 ,  G06F13/16 ,  G06F15/17 ,  G06F13/14

Abstract: PO9-90-032 SPLIT INSTRUCTION PAGING METHOD AND MEANS Asynchronously transfers blocks of data (called pages) between two different electronic media of a data processing system. The different media may be a system main storage and a system expanded storage or a non-volatile external type of storage, either of which use different addressing than the main storage. All of these storages may be made of DRAM or SRAM technology with battery backup when necessary. The invention splits the involvement of a program requesting a page transfer into a pair of instructions per page transfer executing on one or more central processors. The first instruction of a pair starts another processor that controls the asynchronous page transfer, and the second instruction of the pair enables the communication of the end of the page transfer to the program. Neither instruction in the pair interrupts the program for the page transfer. A processor executing the starting instruction is immediately free to execute any other available instructions. Although both instructions in a pair may be executed by one processor, the pair may be executed by separate processors. And the execution of other instructions may overlap the page transfer between the execution of the pair.

公开(公告)号：CA2068796A1

公开(公告)日：1993-03-01

申请号：CA2068796

申请日：1992-05-15

Applicant: IBM

Inventor： CHOU NORMAN C ,  GUM PETER H ,  HOUGH ROGER E ,  KIM MOON J ,  MAZUROWSKI JAMES C ,  MCCAULEY DONALD W ,  SCALZI CASPER A ,  SCANLON JOHN F ,  WYMAN LESLIE W

IPC: G06F9/46 ,  G06F9/48 ,  G06F13/26 ,  G06F15/16

Abstract: P09-91-035 CPU EXPANSIVE GRADATION OF I/O INTERRUPTION SUBCLASS RECOGNITION A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.