公开(公告)号：DE2229395A1

公开(公告)日：1974-01-03

申请号：DE2229395

申请日：1972-06-16

Applicant: IBM DEUTSCHLAND

Inventor： ZUEHLKE RAINER DR ING ,  ZIMMERMANN VOLKER DIPL ING

IPC: G11B5/55 ,  G11B21/10

公开(公告)号：DE2916854A1

公开(公告)日：1980-11-06

申请号：DE2916854

申请日：1979-04-26

Applicant: IBM DEUTSCHLAND

Inventor： SCHETTLER HELMUT DIPL ING ,  REMSHARDT ROLF DIPL ING ,  BROSCH RUDOLF DIPL ING ,  ZUEHLKE RAINER DR ING

IPC: H01L27/02 ,  H01L21/70 ,  G11C5/00 ,  H01L23/56 ,  H01L27/10

Abstract: The semiconductor chip integrated circuit with a control amplifier supplying a constant current, has two bipolar NPN transistors (T1, T2) with emitters connected. The collector of one transistor (T2) is connected by a resistance (R3) to the supply voltage (V1) which is directly connected to the other collector. The base of the first transistor (T1) is connected to the base of a third transistor (T3) with a Schottky diode (D1) between its base and collector, forming an input stage. The junction between the resistance (R3) and the second transistor (T2) is also connected to the base of an emitter follower transistor (T5). This has its output connected to two further transistor stages. The circuit may be used with logic or memory chips.

公开(公告)号：DE3677986D1

公开(公告)日：1991-04-11

申请号：DE3677986

申请日：1986-10-21

Applicant: IBM

Inventor： LUDWIG THOMAS DIPL ING ,  SCHETTLER HELMUT DIPL ING ,  ZUEHLKE RAINER DR ING ,  WAGNER OTTO DIPL ING

IPC: H03K4/02 ,  H03G11/00 ,  H03K5/02 ,  H03K6/04 ,  H03K17/16 ,  H03K19/0185 ,  H03G11/08

Abstract: A method for the digital slope control of the output signals of power amplifiers, as well as a power amplifier suitable for carrying out the method as described. One way of representing the actual slope value is via the number of clock pulses applied to a counter during a measuring interval which depends in its duration on the slope. Such a measuring interval is produced by applying the pulses of a ring oscillator containing one of the power amplifiers to another counter until the overflow of the latter. Another mode of representing the actual slope value consists in counting the number of pulses of the ring oscillator during a measuring interval of predetermined duration. Actual and nominal values of the slope are compared. The results of this comparison change the contents of a left/right-shift register. Its parallel outputs influence, via control lines, control inputs of the power amplifiers in order to alter their slope by switching on or off output transistors arranged in parallel with respect to their switching paths.

公开(公告)号：DE68926886D1

公开(公告)日：1996-08-29

申请号：DE68926886

申请日：1989-09-15

Applicant: IBM

Inventor： SCHETTLER HELMUT DIPL ING ,  SCHULZ UWE ,  ZUEHLKE RAINER DR ING

IPC: H01L21/82 ,  G06F17/50 ,  H01L23/14 ,  H01L23/52 ,  H01L23/538

Abstract: A system design for VLSI chips (1,2) arranged on a carrier (3) and the module thus designed is described. In a top-down design system synoptically and simultaneously an electrical circuitry is optimized by designing synoptically the chips and the chip carrier. The overall logic is divided in partitions which fit on chips. A chip placement on the carrier is performed considering minimum overall connection length and providing preferably parallel connection. Input/Output contacts (121 to 221, 131 to 231, 141 to 241) are assigned on chips vis-a-vis each other when they correspond. They are connected by parallel lines. The design of the several chips is done from outside to inside, starting with the assigned I/O contacts. Overall, in combining optimum overall design and optimum chip design, a semiconductor thin film silicon multichip module of high yield and performance is provided. As carrier (3) that is included in the design from the beginning, preferably a thin film passive silicon carrier is used.

公开(公告)号：DE2447673A1

公开(公告)日：1976-04-08

申请号：DE2447673

申请日：1974-10-05

Applicant: IBM DEUTSCHLAND

Inventor： ZUEHLKE RAINER DR ING ,  ZIMMERMANN VOLKER DIPL ING ,  ULLAND HARTMUT DIPL ING

IPC: H02P8/12 ,  G01P3/46 ,  H02P8/14 ,  H02P8/32 ,  H02P8/00

公开(公告)号：DE68926886T2

公开(公告)日：1997-02-06

申请号：DE68926886

申请日：1989-09-15

Applicant: IBM

Inventor： SCHETTLER HELMUT DIPL ING ,  SCHULZ UWE ,  ZUEHLKE RAINER DR ING

IPC: H01L21/82 ,  G06F17/50 ,  H01L23/14 ,  H01L23/52 ,  H01L23/538

Abstract: A system design for VLSI chips (1,2) arranged on a carrier (3) and the module thus designed is described. In a top-down design system synoptically and simultaneously an electrical circuitry is optimized by designing synoptically the chips and the chip carrier. The overall logic is divided in partitions which fit on chips. A chip placement on the carrier is performed considering minimum overall connection length and providing preferably parallel connection. Input/Output contacts (121 to 221, 131 to 231, 141 to 241) are assigned on chips vis-a-vis each other when they correspond. They are connected by parallel lines. The design of the several chips is done from outside to inside, starting with the assigned I/O contacts. Overall, in combining optimum overall design and optimum chip design, a semiconductor thin film silicon multichip module of high yield and performance is provided. As carrier (3) that is included in the design from the beginning, preferably a thin film passive silicon carrier is used.

公开(公告)号：DE3621469A1

公开(公告)日：1988-01-07

申请号：DE3621469

申请日：1986-06-26

Applicant: IBM DEUTSCHLAND

Inventor： SCHETTLER HELMUT DIPL ING ,  VOGEL ARMIN ,  WAGNER OTTO DIPL ING ,  ZUEHLKE RAINER DR ING

IPC: G01R31/30 ,  G01R31/3185 ,  G01R31/28 ,  H01L21/66

Abstract: A multiplicity of gate elements (gate arrays) which are arranged like a matrix are connected by means of their line outputs and by means of their column outputs to an oscillator circuit, whose first output is connected to all the column inputs and whose second output is connected to all the row inputs. In the event of defective gate elements, said elements are localised in that, during the detection of a defective gate element row, the gate element rows orthogonal thereto are selected successively via their address and via a signal data input. The gate element row located in front of and behind a defective gate element row is determined by oscillator loops. The individual gate elements consist of a plurality of gates and make it possible to change a signal flow from a line into a column and vice versa. This makes possible signal flow diversion which simplifies fault localisation and its representation in the course of a display.

公开(公告)号：DE2855724A1

公开(公告)日：1980-07-03

申请号：DE2855724

申请日：1978-12-22

Applicant: IBM DEUTSCHLAND

Inventor： SCHETTLER HELMUT DIPL ING ,  BROSCH RUDOLF DR ING ,  ZUEHLKE RAINER DR ING ,  SCHUMACHER HANS DR RER NAT

IPC: H03K19/0175 ,  G05F1/46 ,  H03K5/00 ,  H03K5/13 ,  H01L21/12 ,  H01L23/56 ,  G06F7/48

Abstract: For equalizing the signal delay times of semiconductor chips a digital control circuit is provided on each chip. By altering the supply voltage, the digital control circuit influences the signal delay times. The digital control circuit comprises a comparator circuit where the signal delay of a clock pulse is compared in a chain of inverters with the very precisely defined clock interval. Depending on the result of the comparison, the count of an up-down counter is incremented or decremented by one. The resulting count is decoded and converted into a corresponding voltage for operating the circuits of the semiconductor chip. Subsequently, the above described steps are repeated until the difference DELTA t between the arrival of a clock pulse delayed by the chain, and the following undelayed clock pulse approaches zero.