-
公开(公告)号:JP2011009742A
公开(公告)日:2011-01-13
申请号:JP2010132935
申请日:2010-06-10
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor: BEHUN J RICHARD , STONE DAVID B
CPC classification number: H01L23/50 , H01L23/49811 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/16 , H01L2224/0401 , H01L2224/05599 , H01L2224/131 , H01L2224/16225 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/19015 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide an electrical property-altering planar member with a solder element in an IC chip package.SOLUTION: A structure includes a solder element 102 for electrically coupling a substrate 104 of an integrated circuit (IC) chip package 106 and a printed circuit board (PCB) 108; and a first electrical property altering, substantially planar member 130C, 130P positioned between the solder element 102 and at least one of a landing pad 120C of the substrate 104 and a landing pad of the PCB 108. In another embodiment, the electrical property altering, planar member 130C, 130P can be applied to the solder element(s) 102 between the IC chip 110 and the package substrate.
Abstract translation: 要解决的问题:在IC芯片封装中提供具有焊料元件的电性能改变的平面构件。解决方案:一种结构包括用于将集成电路(IC)芯片封装106的衬底104电耦合的焊料元件102和 印刷电路板(PCB)108; 以及位于焊料元件102和衬底104的接地焊盘120C和PCB 108的着陆焊盘之中的至少一个之间的第一电性质改变的基本平坦的构件130C,130P。在另一个实施例中, 平面构件130C,130P可以被施加到IC芯片110和封装衬底之间的焊料元件102。
-
公开(公告)号:GB2501853A
公开(公告)日:2013-11-06
申请号:GB201314831
申请日:2012-01-16
Applicant: IBM
Inventor: LACROIX LUKE D , LAMOREY MARK C H , OAKLAND STEVEN F , PATEL JANAK G , PFARR KERRY P , SLOTA PETER , STONE DAVID B
Abstract: Detection circuits, methods of use and manufacture and design structures are provided herein. The structure (25) includes at least one signal line (30) traversing one or more metal layers (20) of an integrated circuit. Circuitry (35) is coupled to the at least one signal line, which is structured to receive a signal with a known signal value (VDD) from the at least one signal line or a signal from a different potential (GND) and, based on which signal is received; determine whether there is a structural defect in the integrated circuit.
-