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    1.
    发明专利
    未知

    公开(公告)号：DE69022864D1

    公开(公告)日：1995-11-16

    申请号：DE69022864

    申请日：1990-01-15

    Applicant: IBM

    Inventor： HARAME DAVID L ,  PATTON GARY L ,  STORK JOHANNES M C

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/82 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/732 ,  H01L27/08

    Abstract: A transistor structure including a complementary pair of vertical bipolar transistors on a common semiconductor substrate. A first epitaxial layer (12) of semiconductor material of a first conductivity type is formed on the surface of a semiconductor substrate (10) of a second conductivity type, and a sub-emitter region for one of said complementary transistors being formed in said first layer (12). A sub-collector region (14) of a second conductivity type for the other of said complementary transistors is formed in the first layer (12). A second epitaxial layer (16) of semiconductor material of said second conductivity type is formed on the surface of said first layer (12). A third epitaxial layer (18) of semiconductor material of said first conductivity type is formed on the surface of said second layer (16). Deep recessed isolation regions (30, 32, 34) extend from the surface of said third layer (18) into said substrate (10), said deep isolation regions surround each of said transistors. Intrinsic base and collector regions (54, 56) of said one transistor are formed in said second and third layers (16, 18) respectively and intrinsic collector and base regions (58, 60) of said other transistor are formed in said second and third layers (16, 18) respectively. Shallow recessed isolation regions (44, 46, 48, 50, 52) are formed in said second and third layers (16, 18) surrounding said intrinsic base and collector regions (54, 58). A pair of extrinsic base regions (76, 78) of said first conductivity type for said other transistor and an extrinsic collector region (72) of said first conductivity type for said one transistor are formed on the surface of said third layer (18). An emitter reach-through region (74) of said first conductivity type is formed in said second and third layers (16, 18). An extrinsic base region (92) of said second conductivity type for said one transistor overlies said collector region (56) of said first conductivity type. A sub-collector reach-through region (94) of said second conductivity type is formed in said second and third layers (16, 18), and an emitter region (96) of said second conductivity type for said other transistor is formed overlying said base region (60) of said first conductivity type.

    3.
    发明专利
    未知

    公开(公告)号：DE69231310T2

    公开(公告)日：2001-02-15

    申请号：DE69231310

    申请日：1992-10-12

    Applicant: IBM

    Inventor： CRABBE EMMANUEL F ,  HARAME DAVID L ,  MEYERSON BERNARD S ,  PATTON GARY ,  STORK JOHANNES M C

    IPC: H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/737

    Abstract: A heterojunction bipolar transistor having a single-crystal emitter with reduced charge storage and acceptable current gain is described herein. The heterojunction transistor comprises a collector region (604), a base region (606) formed on the collector region, and a single-crystal emitter region (608) grown on the base region (606) by low temperature epitaxy. During the formation of the base region (606), a graded profile of 5-23% germanium is added to the base, as the distance to the collector region (604) decreases, thereby decreasing the base bandgap as it approaches the collector region. Further, during the formation of the emitter region (608), a graded profile of 0-20% germanium is added to the emitter as the distance from the emitter-base junction increases. Thus, the emitter bandgap decreases as it moves farther from the emitter-base junction. The result of the above grading profiles is that the emitter bandgap is narrower at the emitter contact than the base bandgap at the emitter-base junction.

    4.
    发明专利
    未知

    公开(公告)号：DE69022864T2

    公开(公告)日：1996-05-30

    申请号：DE69022864

    申请日：1990-01-15

    Applicant: IBM

    Inventor： HARAME DAVID L ,  PATTON GARY L ,  STORK JOHANNES M C

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/82 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/732 ,  H01L27/08

    Abstract: A transistor structure including a complementary pair of vertical bipolar transistors on a common semiconductor substrate. A first epitaxial layer (12) of semiconductor material of a first conductivity type is formed on the surface of a semiconductor substrate (10) of a second conductivity type, and a sub-emitter region for one of said complementary transistors being formed in said first layer (12). A sub-collector region (14) of a second conductivity type for the other of said complementary transistors is formed in the first layer (12). A second epitaxial layer (16) of semiconductor material of said second conductivity type is formed on the surface of said first layer (12). A third epitaxial layer (18) of semiconductor material of said first conductivity type is formed on the surface of said second layer (16). Deep recessed isolation regions (30, 32, 34) extend from the surface of said third layer (18) into said substrate (10), said deep isolation regions surround each of said transistors. Intrinsic base and collector regions (54, 56) of said one transistor are formed in said second and third layers (16, 18) respectively and intrinsic collector and base regions (58, 60) of said other transistor are formed in said second and third layers (16, 18) respectively. Shallow recessed isolation regions (44, 46, 48, 50, 52) are formed in said second and third layers (16, 18) surrounding said intrinsic base and collector regions (54, 58). A pair of extrinsic base regions (76, 78) of said first conductivity type for said other transistor and an extrinsic collector region (72) of said first conductivity type for said one transistor are formed on the surface of said third layer (18). An emitter reach-through region (74) of said first conductivity type is formed in said second and third layers (16, 18). An extrinsic base region (92) of said second conductivity type for said one transistor overlies said collector region (56) of said first conductivity type. A sub-collector reach-through region (94) of said second conductivity type is formed in said second and third layers (16, 18), and an emitter region (96) of said second conductivity type for said other transistor is formed overlying said base region (60) of said first conductivity type.

    6.
    发明专利
    未知

    公开(公告)号：DE69231310D1

    公开(公告)日：2000-09-07

    申请号：DE69231310

    申请日：1992-10-12

    Applicant: IBM

    Inventor： CRABBE EMMANUEL F ,  HARAME DAVID L ,  MEYERSON BERNARD S ,  PATTON GARY ,  STORK JOHANNES M C

    IPC: H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/737

    Abstract: A heterojunction bipolar transistor having a single-crystal emitter with reduced charge storage and acceptable current gain is described herein. The heterojunction transistor comprises a collector region (604), a base region (606) formed on the collector region, and a single-crystal emitter region (608) grown on the base region (606) by low temperature epitaxy. During the formation of the base region (606), a graded profile of 5-23% germanium is added to the base, as the distance to the collector region (604) decreases, thereby decreasing the base bandgap as it approaches the collector region. Further, during the formation of the emitter region (608), a graded profile of 0-20% germanium is added to the emitter as the distance from the emitter-base junction increases. Thus, the emitter bandgap decreases as it moves farther from the emitter-base junction. The result of the above grading profiles is that the emitter bandgap is narrower at the emitter contact than the base bandgap at the emitter-base junction.

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