公开(公告)号：GB2455212A

公开(公告)日：2009-06-03

申请号：GB0823157

申请日：2008-12-19

Applicant: IBM

Inventor： GERWIG GUENTER ,  MAYER ULRICH ,  LEHNERT FRANK ,  SWANEY SCOTT BARNETT ,  WOERNER ALEXANDER ,  KRAUCH ULRICH

IPC: G06F11/10

Abstract: When a central processing unit (CPU) writes processor status to a register file 22, an error correction code is generated 20,21 from the word write selection 12,13, the register file write selection 10, the register file write address 11 and the write data 14,15. The error correction code is stored with the data in the register file. When the data is read back, an error correction code is generated from the word read selection, the register file read selection, the register file read address and the read data. This is compared with the value which was stored when the data was written. Any difference signifies an error. The processor status may be stored in the register file as two separate words with separate error correction codes. In this case, the high and low words are selected using the word write selection and the word read selection.

公开(公告)号：GB2456656B

公开(公告)日：2012-11-07

申请号：GB0822778

申请日：2008-12-15

Applicant: IBM

Inventor： MAYER ULRICH ,  LEHNERT FRANK ,  GERWIG GUENTER ,  SWANEY SCOTT BARNETT

IPC: G06F11/07 ,  G06F9/38

公开(公告)号：GB2455212B

公开(公告)日：2012-03-21

申请号：GB0823157

申请日：2008-12-19

Applicant: IBM

Inventor： GERWIG GUENTER ,  MAYER ULRICH ,  LEHNERT FRANK ,  SWANEY SCOTT BARNETT ,  WOERNER ALEXANDER ,  KRAUCH ULRICH

IPC: G06F11/10

公开(公告)号：GB2456656A

公开(公告)日：2009-07-29

申请号：GB0822778

申请日：2008-12-15

Applicant: IBM

Inventor： MAYER ULRICH ,  LEHNERT FRANK ,  GERWIG GUENTER ,  SWANEY SCOTT BARNETT

IPC: G06F11/07 ,  G06F9/38

Abstract: The invention relates to apparatus for controlling timeouts and delays of an error recovery procedure in a digital circuit, e.g. a microprocessor. The apparatus comprises a finite state machine (FSM) 10, having a plurality of states 12 and a plurality of transitions 14. Transitions 14 are arranged between two states 12 respectively. States 12 correspond with operation steps (40, 44, 52, 56, 58, 64) of the error recovery procedure, including error classification, a drain operation, a fence operation in which a microprocessor core does not communicate with memory, a reset or refresh operation, and automatic built-in self test (ABIST). Transitions 14 of the FSM 10 depend on conditions (46, 50, 53, 57, 59, 62) for the error recovery procedure. The FSM 10 is coupled with a timeout logic circuit 20 which controls a timer to obtain the timeouts (46, 53, 57, 59) of the error recovery procedure. The FSM is configurable by a data vector which describes states 12 of the FSM for which the timer should be engaged.