公开(公告)号：DE69023467D1

公开(公告)日：1995-12-14

申请号：DE69023467

申请日：1990-09-03

Applicant: IBM

Inventor： BUTLER EDWARD ,  ELLIS WAYNE FREDERICK ,  REDMAN THEODORE MILTON ,  THOMA ENDRE PHILIP

IPC: G11C29/00 ,  G11C8/08 ,  G11C11/401 ,  G11C11/407 ,  G11C29/50 ,  G11C8/00

公开(公告)号：DE3175267D1

公开(公告)日：1986-10-09

申请号：DE3175267

申请日：1981-10-09

Applicant: IBM

Inventor： THOMA ENDRE PHILIP

IPC: G11C11/401 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/24

Abstract: Memory system comprising dynamic memory cells, wherein each cell comprises a switchable cell device (10) and a capacitive node (12), wherein said switchable cell device [10) is connected to a bit line (14) to read the charge stored at said (12) node and to a first word line (16) to selectively switch said cell device (10) responsive to a first signal in said word line (16).Means are provided for rewriting the cell after reading without discharging the bit line to thereby improve cycle time. The cell includes an independently operated device (24) to access the capacitive storage node (12) to discharge the node of any charge thereon after the reading of a low or no charge bit on the capacitive storage node.

公开(公告)号：DE69023467T2

公开(公告)日：1996-06-20

申请号：DE69023467

申请日：1990-09-03

Applicant: IBM

Inventor： BUTLER EDWARD ,  ELLIS WAYNE FREDERICK ,  REDMAN THEODORE MILTON ,  THOMA ENDRE PHILIP

IPC: G11C29/00 ,  G11C8/08 ,  G11C11/401 ,  G11C11/407 ,  G11C29/50 ,  G11C8/00

公开(公告)号：DE69022975D1

公开(公告)日：1995-11-16

申请号：DE69022975

申请日：1990-11-17

Applicant: IBM

Inventor： BUSCH ROBERT EDWARD ,  HOVIS WILLIAM PAUL ,  REDMAN THEODORE MILTON ,  THOMA ENDRE PHILIP ,  YANKOSKY JAMES ANDREW

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C7/00 ,  G11C11/409 ,  G11C11/407

Abstract: A method and device for setting at lease three operating modes of a memory device is provided. The voltage signal is sensed at a first input and an enable signal is sensed at a second input. When an enable signal is received at a second input the memory device operates at the first operating mode if the voltage state at the first input is low; it operates at a second mode if the voltage state at the second is high; and it operates at a third operating mode if the voltage at the first input changes after the enable signal is received at the input. Also a four mode operation can be achieved.

公开(公告)号：DE3882278T2

公开(公告)日：1994-02-17

申请号：DE3882278

申请日：1988-04-19

Applicant: IBM

Inventor： BUSCH ROBERT EDWARD ,  THOMA ENDRE PHILIP

IPC: G11C11/401 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C7/00 ,  G11C11/409

Abstract: A dual sense amplifier construction with divided bit line isolation. A switch is disposed at approximately the midpoint of a bit line to divide the bit line into first and second bit line segments. When opened, the switch provides electrical isolation between the first and second bit line segments so that an accessed memory charge can be isolated from one-half of the capacitance associated with the bit line. Once the isolated memory charge is read and pre-amplified, the remaining bit line capacitance is no longer of concern. The switch is then closed to provide electrical connection between the first and second bit line segments, thereby allowing the completion of the amplification operation.

公开(公告)号：DE69022975T2

公开(公告)日：1996-05-30

申请号：DE69022975

申请日：1990-11-17

Applicant: IBM

Inventor： BUSCH ROBERT EDWARD ,  HOVIS WILLIAM PAUL ,  REDMAN THEODORE MILTON ,  THOMA ENDRE PHILIP ,  YANKOSKY JAMES ANDREW

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C7/00 ,  G11C11/409 ,  G11C11/407

Abstract: A method and device for setting at lease three operating modes of a memory device is provided. The voltage signal is sensed at a first input and an enable signal is sensed at a second input. When an enable signal is received at a second input the memory device operates at the first operating mode if the voltage state at the first input is low; it operates at a second mode if the voltage state at the second is high; and it operates at a third operating mode if the voltage at the first input changes after the enable signal is received at the input. Also a four mode operation can be achieved.

公开(公告)号：DE3882278D1

公开(公告)日：1993-08-19

申请号：DE3882278

申请日：1988-04-19

Applicant: IBM

Inventor： BUSCH ROBERT EDWARD ,  THOMA ENDRE PHILIP

IPC: G11C11/401 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C7/00 ,  G11C11/409

Abstract: A dual sense amplifier construction with divided bit line isolation. A switch is disposed at approximately the midpoint of a bit line to divide the bit line into first and second bit line segments. When opened, the switch provides electrical isolation between the first and second bit line segments so that an accessed memory charge can be isolated from one-half of the capacitance associated with the bit line. Once the isolated memory charge is read and pre-amplified, the remaining bit line capacitance is no longer of concern. The switch is then closed to provide electrical connection between the first and second bit line segments, thereby allowing the completion of the amplification operation.