公开(公告)号：DE69022975T2

公开(公告)日：1996-05-30

申请号：DE69022975

申请日：1990-11-17

Applicant: IBM

Inventor： BUSCH ROBERT EDWARD ,  HOVIS WILLIAM PAUL ,  REDMAN THEODORE MILTON ,  THOMA ENDRE PHILIP ,  YANKOSKY JAMES ANDREW

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C7/00 ,  G11C11/409 ,  G11C11/407

Abstract: A method and device for setting at lease three operating modes of a memory device is provided. The voltage signal is sensed at a first input and an enable signal is sensed at a second input. When an enable signal is received at a second input the memory device operates at the first operating mode if the voltage state at the first input is low; it operates at a second mode if the voltage state at the second is high; and it operates at a third operating mode if the voltage at the first input changes after the enable signal is received at the input. Also a four mode operation can be achieved.

公开(公告)号：DE3882278D1

公开(公告)日：1993-08-19

申请号：DE3882278

申请日：1988-04-19

Applicant: IBM

Inventor： BUSCH ROBERT EDWARD ,  THOMA ENDRE PHILIP

IPC: G11C11/401 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C7/00 ,  G11C11/409

Abstract: A dual sense amplifier construction with divided bit line isolation. A switch is disposed at approximately the midpoint of a bit line to divide the bit line into first and second bit line segments. When opened, the switch provides electrical isolation between the first and second bit line segments so that an accessed memory charge can be isolated from one-half of the capacitance associated with the bit line. Once the isolated memory charge is read and pre-amplified, the remaining bit line capacitance is no longer of concern. The switch is then closed to provide electrical connection between the first and second bit line segments, thereby allowing the completion of the amplification operation.

公开(公告)号：SG67961A1

公开(公告)日：1999-10-19

申请号：SG1996010871

申请日：1996-10-16

Applicant: IBM

Inventor： BUSCH ROBERT EDWARD ,  ZICK KENNETH MICHAEL ,  HOULE ROBERT MAURICE

IPC: G06F1/10 ,  H03L7/18 ,  H04J3/06 ,  H04L7/033

Abstract: A circuit for synchronizing a multiplied system clock signal includes a device for generating a system clock signal, a first device that receives the system clock signal and generates a synchronization signal and at least one second device that receives the system clock signal and the synchronization signal. Each of the second devices includes a device for multiplying the system clock signal to produce the multiplied system clock signal and a device for synchronizing the multiplied system clock signal with each other multiplied system clock signal produced by the other second devices based on the synchronization signal.

公开(公告)号：DE69022975D1

公开(公告)日：1995-11-16

申请号：DE69022975

申请日：1990-11-17

Applicant: IBM

Inventor： BUSCH ROBERT EDWARD ,  HOVIS WILLIAM PAUL ,  REDMAN THEODORE MILTON ,  THOMA ENDRE PHILIP ,  YANKOSKY JAMES ANDREW

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C7/00 ,  G11C11/409 ,  G11C11/407

Abstract: A method and device for setting at lease three operating modes of a memory device is provided. The voltage signal is sensed at a first input and an enable signal is sensed at a second input. When an enable signal is received at a second input the memory device operates at the first operating mode if the voltage state at the first input is low; it operates at a second mode if the voltage state at the second is high; and it operates at a third operating mode if the voltage at the first input changes after the enable signal is received at the input. Also a four mode operation can be achieved.

公开(公告)号：DE3882278T2

公开(公告)日：1994-02-17

申请号：DE3882278

申请日：1988-04-19

Applicant: IBM

Inventor： BUSCH ROBERT EDWARD ,  THOMA ENDRE PHILIP

IPC: G11C11/401 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C7/00 ,  G11C11/409

Abstract: A dual sense amplifier construction with divided bit line isolation. A switch is disposed at approximately the midpoint of a bit line to divide the bit line into first and second bit line segments. When opened, the switch provides electrical isolation between the first and second bit line segments so that an accessed memory charge can be isolated from one-half of the capacitance associated with the bit line. Once the isolated memory charge is read and pre-amplified, the remaining bit line capacitance is no longer of concern. The switch is then closed to provide electrical connection between the first and second bit line segments, thereby allowing the completion of the amplification operation.