公开(公告)号：DE69123372D1

公开(公告)日：1997-01-16

申请号：DE69123372

申请日：1991-01-24

Applicant: IBM

Inventor： BARTH JOHN EDWARD ,  DRAKE CHARLES EDWARD ,  FIFIELD JOHN ATKINSON ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  STAPPER CHARLES HENRI ,  YANKOSKY JAMES ANDREW

IPC: G11C11/401 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G06F11/20

Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：DE69022975D1

公开(公告)日：1995-11-16

申请号：DE69022975

申请日：1990-11-17

Applicant: IBM

Inventor： BUSCH ROBERT EDWARD ,  HOVIS WILLIAM PAUL ,  REDMAN THEODORE MILTON ,  THOMA ENDRE PHILIP ,  YANKOSKY JAMES ANDREW

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C7/00 ,  G11C11/409 ,  G11C11/407

Abstract: A method and device for setting at lease three operating modes of a memory device is provided. The voltage signal is sensed at a first input and an enable signal is sensed at a second input. When an enable signal is received at a second input the memory device operates at the first operating mode if the voltage state at the first input is low; it operates at a second mode if the voltage state at the second is high; and it operates at a third operating mode if the voltage at the first input changes after the enable signal is received at the input. Also a four mode operation can be achieved.

公开(公告)号：DE69119258T2

公开(公告)日：1996-11-21

申请号：DE69119258

申请日：1991-01-19

Applicant: IBM

Inventor： BARTH JOHN EDWARD ,  DRAKE CHARLES EDWARD ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  KELLEY GORDON ARTHUR ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  YANKOSKY JAMES ANDREW

IPC: G11C11/41 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C8/00

Abstract: Low power addressing systems are provided which include a given number of memory segments (26, 28, 30, 32, 34, 38), each having word and bit/sense lines, a given number of decoders (42, 44, 46, 48, 50, 52, 54, 56) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one word line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a first plurality of transmission gate systems (58, 60, 62, 64), each having first (92) and second (94) transmission gates, with each of the gates being coupled to a different one of the decoders (42, 44, 46, 48, 50, 52, 56), a second decoder (66) having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems (58, 60, 62, 64), first control circuits for selectively activating the first (92) and second (94) gates in each of the first plurality of transmission gate systems (58, 60, 62, 64), a third given number of decoders (68, 70, 72, 74, 76, 80, 82) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one bit/sense line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a second plurality of transmission gate systems (84, 86, 88, 90), each having first (102) and second (104) transmission gates, with each of the gates of the second plurality of transmission gate systems (84, 86, 88, 90) being coupled to a different one of the third given number of decoders (26, 28, 30, 32, 34, 36, 38), and second control circuits for selectively activating the first (102) and second (104) gates of each of the third plurality of transmission gate systems (26, 28, 30, 32, 34, 36, 38).

公开(公告)号：DE69119258D1

公开(公告)日：1996-06-13

申请号：DE69119258

申请日：1991-01-19

Applicant: IBM

Inventor： BARTH JOHN EDWARD ,  DRAKE CHARLES EDWARD ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  KELLEY GORDON ARTHUR ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  YANKOSKY JAMES ANDREW

IPC: G11C11/41 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C8/00

Abstract: Low power addressing systems are provided which include a given number of memory segments (26, 28, 30, 32, 34, 38), each having word and bit/sense lines, a given number of decoders (42, 44, 46, 48, 50, 52, 54, 56) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one word line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a first plurality of transmission gate systems (58, 60, 62, 64), each having first (92) and second (94) transmission gates, with each of the gates being coupled to a different one of the decoders (42, 44, 46, 48, 50, 52, 56), a second decoder (66) having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems (58, 60, 62, 64), first control circuits for selectively activating the first (92) and second (94) gates in each of the first plurality of transmission gate systems (58, 60, 62, 64), a third given number of decoders (68, 70, 72, 74, 76, 80, 82) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one bit/sense line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a second plurality of transmission gate systems (84, 86, 88, 90), each having first (102) and second (104) transmission gates, with each of the gates of the second plurality of transmission gate systems (84, 86, 88, 90) being coupled to a different one of the third given number of decoders (26, 28, 30, 32, 34, 36, 38), and second control circuits for selectively activating the first (102) and second (104) gates of each of the third plurality of transmission gate systems (26, 28, 30, 32, 34, 36, 38).

公开(公告)号：SG43875A1

公开(公告)日：1997-11-14

申请号：SG1996003608

申请日：1991-01-24

Applicant: IBM

Inventor： BARTH JOHN EDWARD JR ,  DRAKE CHARLES EDWARD ,  FIFIELD JOHN ATKINSON ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  STAPPER CHARLES HENRI ,  YANKOSKY JAMES ANDREW

IPC: G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G11C11/401 ,  G06F11/20

Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：HK62097A

公开(公告)日：1997-05-16

申请号：HK62097

申请日：1997-05-08

Applicant: IBM

Inventor： BARTH JOHN EDWARD JR ,  DRAKE CHARLES EDWARD ,  FIFIELD JOHN ATKINSON ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  STAPPER CHARLES HENRI ,  YANKOSKY JAMES ANDREW

IPC: G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G11C11/401 ,  G06F11/20

Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：DE69022975T2

公开(公告)日：1996-05-30

申请号：DE69022975

申请日：1990-11-17

Applicant: IBM

Inventor： BUSCH ROBERT EDWARD ,  HOVIS WILLIAM PAUL ,  REDMAN THEODORE MILTON ,  THOMA ENDRE PHILIP ,  YANKOSKY JAMES ANDREW

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C7/00 ,  G11C11/409 ,  G11C11/407

Abstract: A method and device for setting at lease three operating modes of a memory device is provided. The voltage signal is sensed at a first input and an enable signal is sensed at a second input. When an enable signal is received at a second input the memory device operates at the first operating mode if the voltage state at the first input is low; it operates at a second mode if the voltage state at the second is high; and it operates at a third operating mode if the voltage at the first input changes after the enable signal is received at the input. Also a four mode operation can be achieved.