公开(公告)号：JP2004167671A

公开(公告)日：2004-06-17

申请号：JP2003348877

申请日：2003-10-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KOCIS JOSEPH T ,  TORNELLO JAMES ,  PETRARCA KEVIN ,  VOLANT RICHARD ,  SUBANNA SESHADRI

IPC: B81C1/00 ,  B81B3/00 ,  H01H50/00

CPC classification number: B81C1/00666 ,  B81B2201/014 ,  B81C2201/0167 ,  H01F2007/068 ,  H01H50/005

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing an encapsulated micro electro-mechanical system (MEMS) which causes little metallic fatigue and stress.
SOLUTION: The MEMS manufacturing method includes steps for forming a dielectric layer 204, patterning the upper surface of the first dielectric layer 204 to form a trench, forming a release material 212 in the trench, patterning the upper surface of the release material 212 to form the other trench, forming a first encapsulating layer 222 that includes sidewalls in the other trench, forming a core layer 242 in the first encapsulating layer 222, and forming a second encapsulating layer 262 above the core layer 242 where the second encapsulating layer 262 is connected to sidewalls of the first encapsulating layer 222.
COPYRIGHT: (C)2004,JPO

公开(公告)号：AT550784T

公开(公告)日：2012-04-15

申请号：AT10700729

申请日：2010-01-08

Applicant: IBM

Inventor： ANDRY PAUL ,  TSANG CORNELIA ,  SPROGIS EDMUND ,  COTTE JOHN ,  TORNELLO JAMES ,  LOFARO MICHAEL

IPC: H01L21/768 ,  H01L23/48

Abstract: An assembly including a main wafer having a body with a front side and a back side and a plurality of blind electrical vias terminating above the back side, and a handler wafer, is obtained. A step includes exposing the blind electrical vias to various heights on the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side.