公开(公告)号：EP1800335A4

公开(公告)日：2008-01-02

申请号：EP05797431

申请日：2005-09-20

Applicant: IBM

Inventor： PETRARCA KEVIN S ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL ,  RODBELL KENNETH P

IPC: H01L21/31 ,  H01L21/44 ,  H01L21/469 ,  H01L21/4763

CPC classification number: H01L21/76873 ,  H01L21/2855 ,  H01L21/7684 ,  H01L21/76877

Abstract: Defects on the edge of copper interconnects for back end of the line semiconductor devices are alleviated by an interconnect that comprises an impure copper seed layer (440). The impure copper seed layer (440) covers a barrier layer (230), which covers an insulating layer (115) that has an opening. Electroplated copper fills the opening in the insulating layer (115). Through a chemical mechanical polish, the barrier layer (230), the impure copper seed layer (440) derived from an electroplated copper bath, and the electroplated copper are planarized to the insulating layer (115).

公开(公告)号：JP2003109918A

公开(公告)日：2003-04-11

申请号：JP2001300046

申请日：2001-09-28

Applicant: IBM

Inventor： CANAPERI DONALD F ,  COHEN GUY ,  RYAN HAN ,  OTT JOHN A ,  LOFARO MICHAEL ,  CHU JACK O

IPC: B24B37/00 ,  C08J5/14 ,  C09K3/14 ,  H01L21/304

Abstract: PROBLEM TO BE SOLVED: To provide a method and device by which a semiconductor substrate, a CMP tool, a brush cleaning tool, and a chemical wafer cleaning tool can be incorporated. SOLUTION: CMP is performed with a descending force of 1 psi, backward air pressure of 0.5 psi, platen speed of 50 rpm, carrier speed of 30 rpm, and slurry flow rate of 140 milliliter.

公开(公告)号：AT550784T

公开(公告)日：2012-04-15

申请号：AT10700729

申请日：2010-01-08

Applicant: IBM

Inventor： ANDRY PAUL ,  TSANG CORNELIA ,  SPROGIS EDMUND ,  COTTE JOHN ,  TORNELLO JAMES ,  LOFARO MICHAEL

IPC: H01L21/768 ,  H01L23/48

Abstract: An assembly including a main wafer having a body with a front side and a back side and a plurality of blind electrical vias terminating above the back side, and a handler wafer, is obtained. A step includes exposing the blind electrical vias to various heights on the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side.