公开(公告)号：AT550784T

公开(公告)日：2012-04-15

申请号：AT10700729

申请日：2010-01-08

Applicant: IBM

Inventor： ANDRY PAUL ,  TSANG CORNELIA ,  SPROGIS EDMUND ,  COTTE JOHN ,  TORNELLO JAMES ,  LOFARO MICHAEL

IPC: H01L21/768 ,  H01L23/48

Abstract: An assembly including a main wafer having a body with a front side and a back side and a plurality of blind electrical vias terminating above the back side, and a handler wafer, is obtained. A step includes exposing the blind electrical vias to various heights on the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side.

公开(公告)号：AT445034T

公开(公告)日：2009-10-15

申请号：AT03783387

申请日：2003-11-14

Applicant: IBM

Inventor： ECONOMIKOS LAERTIS ,  DELIGIANNI HARIKLIA ,  COTTE JOHN ,  GRABARZ HENRY ,  CHEN BOMY

IPC: C25D5/22 ,  C25D5/48 ,  C25D7/12 ,  C25D17/00 ,  H01L21/288 ,  H01L21/321 ,  H01L21/768

Abstract: A method and apparatus are described for performing both electroplating of a metal layer and planarization of the layer on a substrate. Electroplating and electroetching of metal (such as copper) are performed in a repeated sequence, followed by chemical-mechanical polishing. An electroplating solution, electroetching solution, and a non-abrasive slurry are dispensed on a polishing pad in the respective process steps. The substrate is held against the pad with a variable force in accordance with the process, so that the spacing between substrate and pad may be less during electroplating than during electroetching.

公开(公告)号：AU2021399002B2

公开(公告)日：2025-02-06

申请号：AU2021399002

申请日：2021-12-13

Applicant: IBM

Inventor： ABRAHAM DAVID ,  DIAL OLIVER ,  COTTE JOHN ,  PETRARCA KEVIN SHAWN

IPC: H01L21/768 ,  G06N10/40 ,  H01L23/00 ,  H01L25/065

Abstract: A device (500) comprises a first chip (508) having a first chip front-side and a first chip back-side, a qubit chip (504) having a qubit chip front-side and a qubit chip back-side, the qubit chip front-side operatively coupled to the first chip front-side with a set of bump-bonds (506), a set of through-silicon vias (TSVs) connected to at least one of the first chip back-side or the qubit chip back-side, and a cap wafer (502) that is metal bonded to at least one of the qubit chip back-side or the first chip back-side. Preferably, the qubits and the TSVs are superconducting, and the cap wafer features a cavity that comprises a metal coating on its inside surface for electromagnetic shielding.