公开(公告)号：GB2503442A

公开(公告)日：2014-01-01

申请号：GB201211280

申请日：2012-06-26

Applicant: IBM

Inventor： ECKERT MARTIN ,  SIVIERO CLAUDIO ,  SUPPER JOCHEN ,  WINKEL THOMAS-MICHAEL ,  TORREITER OTTO ANDREAS ,  FRECH ROLAND

IPC: G01R31/08 ,  G01R27/16 ,  G01R31/00

Abstract: A network power fault detection method comprises instructing at least one first network device to temporarily disconnect from a power supply path of a network, and measuring, at a second network device connected to the network, at least one characteristic of the power supply path of the network while the first network device is temporarily disconnected from the network. The measured characteristic may be voltage and/or current from which impedance may be determined. The network device may comprise a receiver 210 coupled to a bus 202 to receive an instruction to disconnect. A switch 220 activates to disconnect the device and a measurement unit 230 measures a property. Impedance is calculated by unit 240 and may be communicated via the bus to another network device. Network topology can be used to determine fault location. The network may be on a vehicle and may be an electrical or optical network.

公开(公告)号：GB2511087A

公开(公告)日：2014-08-27

申请号：GB201303177

申请日：2013-02-22

Applicant: IBM

Inventor： KUNIGKEIT ECKHARD ,  ECKERT MARTIN ,  TRIANNI QUINTINO LORENZO ,  TORREITER OTTO ANDREAS

IPC: H01L21/66

Abstract: A method for electrical testing of a 3D integrated circuit chip stack is described. The 3D integrated circuit chip stack comprises at least a first integrated circuit chip (300) and a second integrated circuit chip (400). The first integrated circuit chip (300) and the second integrated circuit chip (400) are not soldered together for performing electrical testing. The testing improves yield by allowing defective chips to be found prior to soldering of the chip to the IC chip stack. The assembly for holding the IC chips during testing comprises holes 220 in its sidewalls which allow a vacuum to be formed between the chips, creating a mechanical connection between the chips.

公开(公告)号：DE112018002017T5

公开(公告)日：2020-01-23

申请号：DE112018002017

申请日：2018-06-14

Applicant: IBM

Inventor： TORREITER OTTO ANDREAS ,  RODKO DANIEL ,  SCHMIDT HAGEN ,  GENTNER THOMAS

IPC: G01R31/3177

Abstract: Eine auf Hardware beruhende Steuereinheit aktiviert ein System für eine Menge von Taktzyklen und aktiviert selektiv einen Aspekt des Systems für eine Teilmenge der Menge von Taktzyklen. Die Steuereinheit beinhaltet eine Taktzyklusauswahlschaltung zur Ausgabe eines Testauswahlsignals, das die Teilmenge der Menge von Taktzyklen angibt, während derer der Aspekt des Systems aktiviert werden soll, und eine Teststartschaltung zum Empfang des Testauswahlsignals und zur Ausgabe eines Testsignals zum System, um das System für die Menge von Taktzyklen zu aktivieren. Die Steuereinheit beinhaltet außerdem ein UND-Gatter zur Ausgabe eines verknüpften Signals, um auf der Grundlage des Testauswahlsignals den Aspekt des Systems für die Teilmenge der Menge von Taktzyklen zu aktivieren.

公开(公告)号：GB2519752A

公开(公告)日：2015-05-06

申请号：GB201319034

申请日：2013-10-29

Applicant: IBM

Inventor： TORREITER OTTO ANDREAS ,  ECKERT MARTIN ,  ZOELLIN CHRISTIAN

IPC: G11C29/26 ,  G01R31/317 ,  G01R31/3187 ,  G06F11/27 ,  G11C29/12

Abstract: A method and apparatus for performing an array built-in self-test (ABIST) on an electronic circuit 100 comprising a memory 110 with two or more memory arrays 111-115 and two or more array built-in self-test engines 116-120, each engine associated with a different memory array 111-115, and each engine associated with a programmable delay unit DU1-DU5, preferably a dedicated separate delay unit. The disclosed method comprises the following steps: determine at least one delay value (dn) corresponding to an array built-in self-test engine 116-120 and the delay value (dn) depending on the execution time (tdn) for testing the memory array; provide at least one delay value (dn) to the programmable delay unit DU1-DU5; the method continues by delaying the start of the ABIST engine 116-120 depending on the respective delay value (dn). The delay value (dn) may be determined from the test duration (tdn) of an associated memory cell and the maximum of all test durations (tdmax), for example the difference between tdmax and tdn.. The delay values (dn) may also be chosen such that some or all sets of ABIST engines start processing at different times so as to avoid fluctuations and disturbances in supply currents. Preferably the delay times maybe chosen such that all of the ABIST engines terminate or stop at the same point in time (tend) (figure 5). The termination point is monitored by a dedicated monitoring unit. The programmable delay unit(s) DU1-DU5 may be adapted to generate a start signal after expiry of the delay value (dn) in order to start processing of the associated ABIST engine.