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    Method and structure for reducing power noise
    1.
    发明授权
    Method and structure for reducing power noise 失效
    降低功率噪声的方法和结构

    公开(公告)号：US6437252B2

    公开(公告)日：2002-08-20

    申请号：US74145500

    申请日：2000-12-19

    Applicant: IBM

    Inventor： REHM SIMONE ,  FRECH ROLAND ,  KLINK ERICH ,  VIRAG HELMUT ,  WINKEL THOMAS-MICHAEL ,  BECKER WIREN ,  CHAMBERLIN BRUCE ,  MA WAI

    IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42

    CPC classification number: H05K1/113 ,  H05K1/0231 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09472 ,  H05K2201/0979 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913

    Abstract: Described is a method for minimizing switching noise in the high- and mid-frequency range on printed circuit cards or boards by means of a plurality of surface mounted decoupling capacitors. A novel configuration and implementation of capacitor pads including the connecting vias is also presented. As a result the parasitic inductance of the pads and vias can be significantly reduced. Thus the effectiveness of the decoupling capacitors in the mid and high frequency range can be increased, the voltage drop can be reduced and the system performance can be increased. Several design rules for the new pad via configuration lead to the significant reduction of the parasitic inductance. The proposal is especially important for high integrated system designs on boards and cards combined with increased cycle times.

    Abstract translation: 描述了一种通过多个表面安装的去耦电容器来最小化印刷电路板或板上的高频和中频范围内的开关噪声的方法。 还介绍了包括连接通孔的电容器焊盘的新颖配置和实现。 结果，焊盘和通孔的寄生电感可以显着降低。 因此，可以提高中高频区域中的去耦电容器的有效性，可以降低电压降并且可以提高系统性能。 新焊盘通过配置的几个设计规则导致寄生电感的显着减少。 该建议对于板卡和卡上的高集成系统设计以及增加的周期时间尤其重要。

    Locating faults in a network
    3.
    发明专利
    Locating faults in a network 未知

    公开(公告)号：GB2503442A

    公开(公告)日：2014-01-01

    申请号：GB201211280

    申请日：2012-06-26

    Applicant: IBM

    Inventor： ECKERT MARTIN ,  SIVIERO CLAUDIO ,  SUPPER JOCHEN ,  WINKEL THOMAS-MICHAEL ,  TORREITER OTTO ANDREAS ,  FRECH ROLAND

    IPC: G01R31/08 ,  G01R27/16 ,  G01R31/00

    Abstract: A network power fault detection method comprises instructing at least one first network device to temporarily disconnect from a power supply path of a network, and measuring, at a second network device connected to the network, at least one characteristic of the power supply path of the network while the first network device is temporarily disconnected from the network. The measured characteristic may be voltage and/or current from which impedance may be determined. The network device may comprise a receiver 210 coupled to a bus 202 to receive an instruction to disconnect. A switch 220 activates to disconnect the device and a measurement unit 230 measures a property. Impedance is calculated by unit 240 and may be communicated via the bus to another network device. Network topology can be used to determine fault location. The network may be on a vehicle and may be an electrical or optical network.

    5.
    发明专利
    未知

    公开(公告)号：AT467132T

    公开(公告)日：2010-05-15

    申请号：AT07847223

    申请日：2007-11-20

    Applicant: IBM

    Inventor： FRECH ROLAND ,  KLINK ERICH ,  SAALMUELLER JUERGEN

    IPC: G01R31/28 ,  G01R31/02 ,  G01R31/3185 ,  H04B3/46 ,  H04M3/34

    Abstract: A method for determining current return path integrity in an electric device with a plurality of signal lines and supply lines. A library with at least one reference signal pattern of a near end crosstalk signal on a defined signal line arising from an input signal on another defined signal line is provided, a predetermined signal to a selected signal line of the electric device is applied, the near end crosstalk signal on at least one further signal line of the electric device is detected, said near end crosstalk signal is compared with the corresponding reference signal pattern from the library, and if there is a deviation between the near end crosstalk signal and the corresponding reference signal pattern, an information that there is any defect in the electric device is displayed.

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