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    IMPROVED TLB MANAGEMENT FOR REAL-TIME APPLICATIONS
    1.
    发明申请
    IMPROVED TLB MANAGEMENT FOR REAL-TIME APPLICATIONS 审中-公开
    改进TLB管理实时应用程序

    公开(公告)号：WO2004053698A3

    公开(公告)日：2006-01-12

    申请号：PCT/GB0305108

    申请日：2003-11-21

    Applicant: IBM ,  IBM UK

    Inventor： DAY MICHAEL NORMAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  KAHLE JAMES ALLAN ,  TRUONG THUONG QUANG ,  SHIPPY DAVID

    IPC: G06F12/10 ,  G06F12/12

    CPC classification number: G06F12/1027 ,  G06F12/126

    Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.

    Abstract translation: 计算机系统中的存储器管理通过防止地址转换信息的一部分被替换为高速缓冲存储器中的其他类型的地址转换信息而被改进，该高速缓冲存储器被保留用于存储用于CPU更快速访问的这种地址转换信息。 这样，CPU可以识别存储在高速缓存中的地址转换信息的子集。

    SYSTEM AND METHOD FOR COMMUNICATING INSTRUCTIONS AND DATA BETWEEN A PROCESSOR AND EXTERNAL DEVICES
    4.
    发明申请
    SYSTEM AND METHOD FOR COMMUNICATING INSTRUCTIONS AND DATA BETWEEN A PROCESSOR AND EXTERNAL DEVICES 审中-公开
    用于通信处理器和外部设备之间的指令和数据的系统和方法

    公开(公告)号：WO2007020274A3

    公开(公告)日：2007-04-19

    申请号：PCT/EP2006065372

    申请日：2006-08-16

    Applicant: IBM ,  IBM UK ,  DAY MICHAEL NORMAN ,  JOHNS CHARLES RAY ,  LIBERTY JOHN SAMUEL ,  SWANSON TODD ,  TRUONG THUONG QUANG

    Inventor： DAY MICHAEL NORMAN ,  JOHNS CHARLES RAY ,  LIBERTY JOHN SAMUEL ,  SWANSON TODD ,  TRUONG THUONG QUANG

    IPC: G06F13/28 ,  G06F15/163 ,  H04Q3/545

    CPC classification number: G06F13/28

    Abstract: A system and method for communicating instructions and data between a processor and external devices are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power "stall" state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

    Abstract translation: 提供了一种用于在处理器和外部设备之间传送指令和数据的系统和方法。 系统和方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或者没有可用空间来写入对应的寄存器时，处理器处于低功率“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。

    ESTABLISHING COMMAND ORDER IN AN OUT OF ORDER DMA COMMAND QUEUE
    5.
    发明申请
    ESTABLISHING COMMAND ORDER IN AN OUT OF ORDER DMA COMMAND QUEUE 审中-公开
    在无序的DMA命令队列中建立命令顺序

    公开(公告)号：WO2006006084A3

    公开(公告)日：2006-07-20

    申请号：PCT/IB2005003169

    申请日：2005-07-06

    Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

    Inventor： DAY MICHAEL NORMAN ,  JOHNS CHARLES RAY ,  LIU PEICHUN PETER ,  TRUONG THUONG QUANG ,  YAMAZAKI TAKESHI

    IPC: G06F13/28

    CPC classification number: G06F13/28

    Abstract: A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.

    Abstract translation: 提供了一种用于控制存储器访问的方法，装置和计算机程序。 直接存储器访问（DMA）单元在许多总线体系结构中已经司空见惯。 但是，管理有限的系统资源已成为多个DMA单元的挑战。 为了管理生成的大量命令并保留依赖关系，可以使用命令中的嵌入标志或屏障命令。 这些操作可以控制执行命令的顺序，从而保持依赖关系。

    System, method, computer program and device for communicating command parameter between processor and memory flow controller
    6.
    发明专利
    System, method, computer program and device for communicating command parameter between processor and memory flow controller 有权
    系统，方法，计算机程序和用于在处理器和存储器流量控制器之间通信命令参数的设备

    公开(公告)号：JP2007052790A

    公开(公告)日：2007-03-01

    申请号：JP2006221861

    申请日：2006-08-16

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： JOHNS CHARLES RAY ,  SWANSON TODD ,  LIU PEICHUN PETER ,  DAY MICHAEL NORMAN ,  TRUONG THUONG QUANG

    IPC: G06F15/80

    CPC classification number: G06F13/32 ,  G06F13/1642

    Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for communicating command parameters between a processor and a memory flow controller. SOLUTION: This application utilizes a channel interface as a main mechanism for communication between the processor and the memory flow controller. The channel interface provides a channel for executing communication with, for instance, a processor facility, a memory flow control facility, a machine status register, and an external processor interrupt facility. When data to be read from a corresponding register by a blocking channel are not usable or there is no writing space in the corresponding register, the processor is brought into a low-power "stall" state. When the data are made usable or a space is released, the processor is automatically called via communication on the blocking channel. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于在处理器和存储器流控制器之间传送命令参数的系统和方法。 解决方案：本应用程序利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口提供用于执行与例如处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备的通信的通道。 当通过阻塞通道从对应的寄存器读取的数据不可用或在对应的寄存器中没有写入空间时，处理器进入低功率“失速”状态。 当数据可用或释放空间时，通过阻塞通道上的通信自动调用处理器。 版权所有（C）2007，JPO＆INPIT

    DISABLE WRITE BACK ON ATOMIC RESERVED LINE IN A SMALL CACHE SYSTEM
    9.
    发明申请
    DISABLE WRITE BACK ON ATOMIC RESERVED LINE IN A SMALL CACHE SYSTEM 审中-公开
    在小型缓存系统中的原始保留行上禁用写回

    公开(公告)号：WO2006085140A3

    公开(公告)日：2007-08-16

    申请号：PCT/IB2005004003

    申请日：2005-06-09

    Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

    Inventor： KIM ROY MOONSEUK ,  OKAWA YASUKICHI ,  TRUONG THUONG QUANG

    IPC: G06F12/12 ,  G06F9/312 ,  G06F12/00 ,  G06F12/08

    CPC classification number: G06F12/126 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  G06F12/0831

    Abstract: The present invention provides for managing an atomic facility cache write back state machine. A first write back selection is made. A reservation pointer pointing to the reserved line in the atomic facility data array is established. A next write back selection is made. An entry for the reservation pointer from the next write back selection is removed, whereby the valid reservation line is precluded from being selected for the write back. This prevents a modified command from being invalidated.

    Abstract translation: 本发明提供了管理原子设施高速缓存回写状态机。 首先回写选择。 建立指向原子设施数据阵列中保留行的保留指针。 进行下一个回写选择。 去除了来自下一个回写选择的预约指针的条目，从而排除了有效的预留行被选择用于回写。 这样可以防止修改的命令无效。

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