公开(公告)号：EP1371091A4

公开(公告)日：2009-04-01

申请号：EP01990800

申请日：2001-12-04

Applicant: IBM

Inventor： GATES STEPHEN MCCONNELL ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  TYBERG CHRISTY SENSENICH

IPC: H01L23/48 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76835 ,  H01L21/76811 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. The control over the conductor resistance is obtained using a buried etch stop layer (56) having a second atomic composition located between the line and via dielectric layers (54', 58') of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask (60) which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.

公开(公告)号：EP1371090A4

公开(公告)日：2007-10-24

申请号：EP01990106

申请日：2001-12-10

Applicant: IBM

Inventor： GATES STEPHEN MCCONNELL ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  TYBERG CHRISTY SENSENICH

IPC: H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763 ,  H01L23/48

CPC classification number: H01L21/76835 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/76811

Abstract: A metal wiring plus low-k dielectric interconnect structure of the dual damascene-type is provided wherein the conductive metal lines and vias are built into a hybrid low-k dielectric which includes two spun-on dielectrics that have different atomic compositions and at least one of the two spun-on dielectrics is porous. The two spun-on dielectrics used in forming the inventive hybrid low-k dielectric each have a dielectric constant of about 2.6 or less, preferably each dielectric of the hybrid structure has a k of from about 1.2 to about 2.2. By utilizing the inventive hybrid low-k dielectric excellent control over metal line resistance (trench depth) is obtained, without no added cost. This is achieved without the use of a buried etch stop layer, which if present, would be formed between the two spun-on dielectrics. Moreover, the spun-on dielectrics of the hybrid low-k dielectric have distinctly different atomic compositions enabling control over the conductor resistance using the bottom spun-on dielectric (i.e., via dielectric) as an inherent etch stop layer for the upper spun-on dielectric (i.e., line dielectric).

公开(公告)号：JP2002270612A

公开(公告)日：2002-09-20

申请号：JP2002037664

申请日：2002-02-15

Applicant: IBM

Inventor： FORNOF ANN RHEA-HELENE ,  GATES STEPHEN MCCONNELL ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  TYBERG CHRISTY SENSENICH

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/316 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a simple method where cost effect for patterning a mutual connection structure, in which the material subjected to spin-on is used as a hard mask, is high. SOLUTION: By using the material subjected to spin-on processing to the hard mask, a process can be executed by using a single tool, and usage of a single curing step is enhance, which is not normally used in a patterning process of the conventional technique, in which a CVD hard mask is used. Selection of a polishing stop layer (formed on a surface of low k dielectrics), which has permittivity nearly equal to that of dielectrics positioned below is enabled by using spin coating, so that effective permittivity of an obtained structure is not significantly increased. The hard mask used contains, at least two kinds of spin-on dielectric materials having different etching speeds.