公开(公告)号：EP1371091A4

公开(公告)日：2009-04-01

申请号：EP01990800

申请日：2001-12-04

Applicant: IBM

Inventor： GATES STEPHEN MCCONNELL ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  TYBERG CHRISTY SENSENICH

IPC: H01L23/48 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76835 ,  H01L21/76811 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. The control over the conductor resistance is obtained using a buried etch stop layer (56) having a second atomic composition located between the line and via dielectric layers (54', 58') of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask (60) which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.

公开(公告)号：EP1371090A4

公开(公告)日：2007-10-24

申请号：EP01990106

申请日：2001-12-10

Applicant: IBM

Inventor： GATES STEPHEN MCCONNELL ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  TYBERG CHRISTY SENSENICH

IPC: H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763 ,  H01L23/48

CPC classification number: H01L21/76835 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/76811

Abstract: A metal wiring plus low-k dielectric interconnect structure of the dual damascene-type is provided wherein the conductive metal lines and vias are built into a hybrid low-k dielectric which includes two spun-on dielectrics that have different atomic compositions and at least one of the two spun-on dielectrics is porous. The two spun-on dielectrics used in forming the inventive hybrid low-k dielectric each have a dielectric constant of about 2.6 or less, preferably each dielectric of the hybrid structure has a k of from about 1.2 to about 2.2. By utilizing the inventive hybrid low-k dielectric excellent control over metal line resistance (trench depth) is obtained, without no added cost. This is achieved without the use of a buried etch stop layer, which if present, would be formed between the two spun-on dielectrics. Moreover, the spun-on dielectrics of the hybrid low-k dielectric have distinctly different atomic compositions enabling control over the conductor resistance using the bottom spun-on dielectric (i.e., via dielectric) as an inherent etch stop layer for the upper spun-on dielectric (i.e., line dielectric).

公开(公告)号：JP2002270612A

公开(公告)日：2002-09-20

申请号：JP2002037664

申请日：2002-02-15

Applicant: IBM

Inventor： FORNOF ANN RHEA-HELENE ,  GATES STEPHEN MCCONNELL ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  TYBERG CHRISTY SENSENICH

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/316 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a simple method where cost effect for patterning a mutual connection structure, in which the material subjected to spin-on is used as a hard mask, is high. SOLUTION: By using the material subjected to spin-on processing to the hard mask, a process can be executed by using a single tool, and usage of a single curing step is enhance, which is not normally used in a patterning process of the conventional technique, in which a CVD hard mask is used. Selection of a polishing stop layer (formed on a surface of low k dielectrics), which has permittivity nearly equal to that of dielectrics positioned below is enabled by using spin coating, so that effective permittivity of an obtained structure is not significantly increased. The hard mask used contains, at least two kinds of spin-on dielectric materials having different etching speeds.

公开(公告)号：JP2005217420A

公开(公告)日：2005-08-11

申请号：JP2005021358

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDELSTEIN DANIEL C ,  COLBURN MATTHEW E ,  COONEY EDWARD C III ,  DALTON TIMOTHY J ,  FITZSIMMONS JOHN A ,  GAMBINO JEFFREY P ,  HUANG ELBERT E ,  LANE MICHAEL W ,  MCGAHAY VINCENT J ,  NICHOLSON LEE M ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  SANKARAN SUJATHA ,  SHAW THOMAS M ,  SIMON ANDREW H ,  STAMPER ANTHONY K

IPC: H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC classification number: B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device of high strength that lowers an effective dielectric constant k eff , maintains an inter-level vertical capacity in an interconnection at a low level and a manufacturing method of the same. SOLUTION: The method of manufacturing the device comprises a step for providing a structure having an insulating layer 120 of at least one interconnection 130 and a step for forming a sublithographic template mask 150 on the insulating layer. A sublithographic feature 135a is formed in the vicinity of at least one intereconnection by performing etching on the insulating layer through the sublithographic template mask using a selective etching step. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种降低有效介电常数k eff 的高强度半导体器件，将互连中的级间垂直容量保持在低水平，并且制造方法 一样的。 解决方案：制造该器件的方法包括提供具有至少一个互连130的绝缘层120和在绝缘层上形成亚光刻模板掩模150的步骤的结构的步骤。 通过使用选择性蚀刻步骤，通过通过亚光刻模板掩模对绝缘层进行蚀刻，在至少一个相互连接附近形成亚光刻部件135a。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2003218109A

公开(公告)日：2003-07-31

申请号：JP2003003569

申请日：2003-01-09

Applicant: IBM

Inventor： DALTON TIMOTHY J ,  ANAND MINAKSHISUNDARAN B ,  ARMACOST MICHAEL D ,  CHEN SHYNG-TSONG ,  GATES STEPHEN M ,  GRECO STEPHEN E ,  KARECKI SIMON M ,  NITTA SATYANARAYANA V

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a metallic pattern on a low-dielectric constant substrate. SOLUTION: A hard mask including a lower hard mask layer 31 and an upper hard mask layer 20 is prepared. The upper hard mask layer 20 is a sacrifice layer of about 200 Å thick, which is preferably made of high-melting-point nitride. The sacrifice layer functions as a stop layer in the following CMP metal removal process. A resist layer is used to perform patterning. A protection layer 31t is formed on a hard mask, or a non-oxidized resist strip process is used, so as to avoid the damage of oxidization to the lower hard mask layer 31. COPYRIGHT: (C)2003,JPO

公开(公告)号：WO2005122195A3

公开(公告)日：2006-06-22

申请号：PCT/US2005018196

申请日：2005-05-23

Applicant: IBM ,  HUANG ELBERT E ,  KIM HYUNGJUN ,  MILLER ROBERT D ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH

Inventor： HUANG ELBERT E ,  KIM HYUNGJUN ,  MILLER ROBERT D ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH

IPC: H01L21/302 ,  H01G13/00 ,  H01L21/311 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/3121 ,  H01L21/3125 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76837 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Interconnect structures are fabricated by methods that comprise depositing a thin conformal passivation dielectric and/or diffusion barrier cap and/or hard mask by an atomic layer deposition or supercritical fluid based process.

Abstract translation: 通过包括通过原子层沉积或基于超临界流体的方法沉积薄的共形钝化介质和/或扩散阻挡盖和/或硬掩模的方法来制造互连结构。

公开(公告)号：JP2005268783A

公开(公告)日：2005-09-29

申请号：JP2005066836

申请日：2005-03-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COLBURN MATTHEW E ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH

IPC: H01J9/14 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for fabricating a nanocolumnar airbridge structure in a Very-Large Scale Integrated (VLSI) and Ultra-Large Scale Integrated (ULSI) devices, and also to provide high performance packaging. SOLUTION: A method for producing a low k, ultra-low k, and super ultra-low-k multilayer interconnect structures on a substrate, in which the interconnect line structure bodies are separated laterally by a dielectric with vertically oriented nanoscale voids, formed by perforating the voids using sub-optical lithography patterning and etching techniques and closing off the tops of the perforations by a dielectric deposition step. The lines are supported by either solid or patterned dielectric features underneath. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在超大规模集成（VLSI）和超大规模集成（ULSI）装置中制造纳米柱式气桥结构的方法，并且还提供高性能包装。 解决方案：一种用于在衬底上制造低k，超低k和超超低k多层互连结构的方法，其中互连线结构体由具有垂直取向的纳米尺度空隙的电介质横向分离 通过使用亚光学光刻图案和蚀刻技术对空隙进行穿孔而形成，并通过介电沉积步骤封闭穿孔的顶部。 这些线由下面的固体或图案化电介质特征支撑。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2002319621A

公开(公告)日：2002-10-31

申请号：JP2002035811

申请日：2002-02-13

Applicant: IBM

Inventor： GATES STEPHEN MCCONNELL ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  TYBERG CRISTY SENSENICH

IPC: H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide an interconnecting structure containing patterned multilayered spun-on dielectrics, and to provide a method of forming the structure. SOLUTION: The interconnecting structure contains the patterned multilayered spun-on dielectrics 12' formed on the surface of a substrate. The dielectrics 12 are constituted of a lower low-k dielectrics 14', an embedded etch stop layer 16', and an upper low-k dielectric 18'. The dielectrics 14' and 18' have a first composition and the layer 16' has a second composition which is different from the first composition and is covalently coupled with the dielectrics 14' and 18'. The mutual connecting structure also contains a polish stop layer 22' formed on the multilayered spun-on dielectrics 12' and a metal conductive region 34 formed in the dielectrics 12'.

公开(公告)号：JP2005175479A

公开(公告)日：2005-06-30

申请号：JP2004353505

申请日：2004-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN SHYNG-TSONG ,  CHIRAS STEFANIE R ,  COLBURN MATTHEW EARL ,  DALTON TIMOTHY JOSEPH ,  HEDRICK JEFFREY CURTIS ,  HUANG ELBERT EMIN ,  KUMAR KAUSHIK A ,  LANE MICHAEL WAYNE ,  MALONE KELLY ,  NARAYAN CHANDRASEKHAR ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  ROSENBERG ROBERT ,  TYBERG CHRISTY S ,  YU ROY RONGQING

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure which reduces the dielectric constant between conductive lines by providing an air dielectric. SOLUTION: In a multilevel microelectronic integrated circuit, air comprises a permanent line level dielectric, and an ultra-low-k material constitutes a via level dielectric. In the IC structure, air is supplied to the line level after removal of a sacrificial material by clean thermal decomposition and auxiliary diffusion of byproducts through porosities. Optionally, air is also included within porosities in the via level dielectric. By incorporating air into the extension produced in the invention, intralevel and interlevel dielectric values are minimized. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供通过提供空气电介质来降低导线之间的介电常数的结构。 解决方案：在多电平微电子集成电路中，空气包括永久线路电平介质，超低k材料构成通孔级电介质。 在IC结构中，通过清洁的热分解和副产物通过孔隙的辅助扩散除去牺牲材料之后，空气被提供给线路层。 任选地，空气也包括在通孔级电介质中的孔隙中。 通过将空气并入本发明中生产的延伸中，使层内和层间介电值最小化。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004214648A

公开(公告)日：2004-07-29

申请号：JP2003421653

申请日：2003-12-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COLBURN MATTHEW E ,  HUANG ELBERT E ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  SAENGER KATHERINE L

IPC: H01L23/12 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming in-layer and interlayer air bridge structures, in a large scale integrated circuit (VLSI) device, a very large scale integrated circuit (ULSI) device, and a high-performance package. SOLUTION: The method of forming low k (dielectric constant) and ultra-low k multilayer mutual connections on a substrate is provided with a process to form a pair of mutual connection, separated along a side face by an air gap and a support layer in a via level of a dual damascene structure which exists only under a metal wiring, a process to remove a sacrificial dielectric through a holed bridge layer to connect an upper surface of the mutual connection along the side face, a process of executing a multilayer level extraction of the sacrificial layer, a process of sealing the bridge by a controlled method, and a process of reducing the effective dielectric constant of a film holed by using a patterning technology of a quasi-optical lithography. COPYRIGHT: (C)2004,JPO&NCIPI