公开(公告)号：WO0247144A3

公开(公告)日：2003-02-13

申请号：PCT/US0145195

申请日：2001-11-29

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CHEN BOMY A ,  HIRSCH ALEXANDER ,  IYER SUNDAR K ,  ROVEDO NIVO ,  WANN HSING-JEN ,  ZHANG YING

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/7621 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/823418 ,  H01L21/823481

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

Abstract translation: 在源极和漏极之下形成图案化的掩埋绝缘体，通过在身体区域上形成掩模并在要形成源极和漏极的区域中注入一定量的n或p型离子，然后蚀刻STI并蚀刻出植入 区。 光氧化之后是STI中的共形氧化物沉积以及蚀刻区域，从而仅在需要时形成掩埋氧化物。

公开(公告)号：DE60103181D1

公开(公告)日：2004-06-09

申请号：DE60103181

申请日：2001-11-29

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHEN A ,  HIRSCH ALEXANDER ,  IYER UMAR ,  ROVEDO NIVO ,  WANN HSING-JEN ,  ZHANG YING

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

公开(公告)号：GB2409932A

公开(公告)日：2005-07-13

申请号：GB0427899

申请日：2004-12-21

Applicant: IBM

Inventor： KU VICTOR ,  STEEGEN AN ,  WANN HSING-JEN ,  WONG KWONG HON

IPC: H01L21/335 ,  H01L21/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: A method is provided for fabricating a gate structure for a semiconductor device in which the gate structure has an inner spacer. A replacement-gate process is used in which material is removed in a gate region to expose a portion of the substrate; a gate dielectric is formed on the exposed portion of the substrate; and an inner spacer layer is formed overlying the gate dielectric and the dielectric material. A silicon layer is then formed which overlies the inner spacer layer. The structure is then planarized so that portions of the silicon layer and inner spacer layer remain in the gate region. A silicide gate structure is then formed from the silicon; the silicide gate structure is separated from dielectric material surrounding the gate by the inner spacer layer. The semiconductor device may include a first gate region and a second gate region with an interface therebetween, with the inner spacer layer covering the interface. When the device has two gate regions, the process may be used in both gate regions, so as to produce separate silicide structures, with an inner spacer separating the two structures.

公开(公告)号：GB2409932B

公开(公告)日：2006-10-25

申请号：GB0427899

申请日：2004-12-21

Applicant: IBM

Inventor： KU VICTOR ,  STEEGEN AN ,  WANN HSING-JEN ,  WONG KWONG HON

IPC: H01L21/28 ,  H01L21/335 ,  H01L21/04 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: A method is provided for fabricating a gate structure for a semiconductor device in which the gate structure has an inner spacer. A replacement-gate process is used in which material is removed in a gate region to expose a portion of the substrate; a gate dielectric is formed on the exposed portion of the substrate; and an inner spacer layer is formed overlying the gate dielectric and the dielectric material. A silicon layer is then formed which overlies the inner spacer layer. The structure is then planarized so that portions of the silicon layer and inner spacer layer remain in the gate region. A silicide gate structure is then formed from the silicon; the silicide gate structure is separated from dielectric material surrounding the gate by the inner spacer layer. The semiconductor device may include a first gate region and a second gate region with an interface therebetween, with the inner spacer layer covering the interface. When the device has two gate regions, the process may be used in both gate regions, so as to produce separate silicide structures, with an inner spacer separating the two structures.

公开(公告)号：DE60103181T2

公开(公告)日：2005-05-04

申请号：DE60103181

申请日：2001-11-29

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHEN A ,  HIRSCH ALEXANDER ,  IYER UMAR ,  ROVEDO NIVO ,  WANN HSING-JEN ,  ZHANG YING

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.