公开(公告)号：JP2005197753A

公开(公告)日：2005-07-21

申请号：JP2005002906

申请日：2005-01-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KU VICTOR ,  STEEGEN AN ,  WANN HSING-JEN C ,  KWON HON WON

IPC: H01L21/335 ,  H01L21/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/28194 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device gate structure having an internal spacer.
SOLUTION: The manufacturing method includes replacement gate process, in which a part of a substrate is exposed by removing material in a gate region, gate dielectric is formed on an exposed portion of the substrate, and an internal spacer layer which covers the gate dielectric and dielectric material is formed. Next, a silicon layer which covers the internal spacer layer is formed. Next, the formed structure is planarized, and a part of the silicon layer and a part of the internal spacer layer are made to remain in the gate region. Next, a silicide gate structure is formed by using the silicon, and the silicide gate structure is separated from the dielectric material around the gate with the internal spacer layer. The semiconductor device can include a first gate region and a second gate region, between which an interface covered by the internal spacer layer is formed. When the device has two gate regions, separate silicide structures, which are separated with the internal spacer layer, can be generated by applying the above process to both the gate regions.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种具有内部间隔物的半导体器件栅极结构的制造方法。 解决方案：制造方法包括替换栅极工艺，其中通过去除栅极区域中的材料使衬底的一部分暴露，栅极电介质形成在衬底的暴露部分上，并且内部间隔层覆盖 形成栅介质和电介质材料。 接下来，形成覆盖内部间隔层的硅层。 接下来，形成的结构被平坦化，并且使硅层的一部分和内部间隔层的一部分保留在栅极区域中。 接下来，通过使用硅形成硅化物栅极结构，并且利用内部间隔层将硅化物栅极结构与栅极周围的电介质材料分离。 半导体器件可以包括第一栅极区域和第二栅极区域，在其间形成由内部间隔层覆盖的界面。 当器件具有两个栅极区域时，可以通过将上述过程应用于两个栅极区域来产生与内部间隔层分离的分离的硅化物结构。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005197748A

公开(公告)日：2005-07-21

申请号：JP2005001988

申请日：2005-01-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KU VICTOR ,  STEEGEN AN ,  WANN HSING-JEN C

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66583 ,  H01L21/28079 ,  H01L21/28247 ,  H01L21/823835 ,  H01L29/66545

Abstract: PROBLEM TO BE SOLVED: To provide a method of producing one metal replacement gate or two metal replacement gate for a semiconductor device.
SOLUTION: This structure contains silicide contacts with a gate region. A part of a substrate is exposed, by removing a dummy gate structure and a sacrificial gate dielectric, and a gate dielectric is formed on the exposed part. A metal layer is formed so as to cover the gate dielectric and dielectric materials. This metal layer, if it is convenient, can be made of a blanket metal layer covering a device wafer. Next, a silicon layer is formed so as to cover the metal layer. This layer can be also made of a blanket layer. Next, the top face of the dielectric materials is exposed, by performing flatting or etch back process. Other parts of the metal layer and the silicon layer remain in a gate region 11, and there is provided a front surface, having the same plane as the top face of the dielectric materials. Next, there are formed the silicide contacts, which are in contact with the metal layer in the gate region 11.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于半导体器件的一个金属替换栅极或两个金属替代栅极的制造方法。 解决方案：该结构包含与栅极区域的硅化物接触。 通过去除伪栅极结构和牺牲栅极电介质来暴露衬底的一部分，并且在暴露部分上形成栅极电介质。 形成金属层以覆盖栅介质和电介质材料。 如果方便，该金属层可以由覆盖器件晶片的覆盖金属层制成。 接下来，形成硅层以覆盖金属层。 该层也可以由覆盖层制成。 接下来，通过进行平坦化或回蚀加工，使电介质材料的顶面露出。 金属层和硅层的其它部分保留在栅极区域11中，并且设置有与电介质材料的顶面相同平面的前表面。 接下来，形成与栅极区域11中的金属层接触的硅化物触点。版权所有（C）2005，JPO＆NCIPI

公开(公告)号：AT504078T

公开(公告)日：2011-04-15

申请号：AT04780054

申请日：2004-08-04

Applicant: IBM

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN ,  YANG HAINING

IPC: H01L21/336 ,  H01L21/20 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

Abstract: A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

公开(公告)号：GB2409932A

公开(公告)日：2005-07-13

申请号：GB0427899

申请日：2004-12-21

Applicant: IBM

Inventor： KU VICTOR ,  STEEGEN AN ,  WANN HSING-JEN ,  WONG KWONG HON

IPC: H01L21/335 ,  H01L21/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: A method is provided for fabricating a gate structure for a semiconductor device in which the gate structure has an inner spacer. A replacement-gate process is used in which material is removed in a gate region to expose a portion of the substrate; a gate dielectric is formed on the exposed portion of the substrate; and an inner spacer layer is formed overlying the gate dielectric and the dielectric material. A silicon layer is then formed which overlies the inner spacer layer. The structure is then planarized so that portions of the silicon layer and inner spacer layer remain in the gate region. A silicide gate structure is then formed from the silicon; the silicide gate structure is separated from dielectric material surrounding the gate by the inner spacer layer. The semiconductor device may include a first gate region and a second gate region with an interface therebetween, with the inner spacer layer covering the interface. When the device has two gate regions, the process may be used in both gate regions, so as to produce separate silicide structures, with an inner spacer separating the two structures.

公开(公告)号：AT438928T

公开(公告)日：2009-08-15

申请号：AT04786558

申请日：2004-08-20

Applicant: IBM

Inventor： STEEGEN AN ,  KU VICTOR ,  WONG KWONG ,  LI YING ,  NARAYANAN VIJAY ,  CABRAL CYRIL JR ,  JAMISON PAUL

IPC: H01L29/94 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/49

Abstract: A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure is first formed on an etch stop layer provided on a semiconductor substrate. A pair of spacers is provided on sidewalls of the sacrificial gate structure. The sacrificial gate structure is then removed, forming an opening. Subsequently, a metal gate including an first layer of metal such as tungsten, a diffusion barrier such as titanium nitride, and a second layer of metal such as tungsten is formed in the opening between the spacers.

公开(公告)号：GB2409932B

公开(公告)日：2006-10-25

申请号：GB0427899

申请日：2004-12-21

Applicant: IBM

Inventor： KU VICTOR ,  STEEGEN AN ,  WANN HSING-JEN ,  WONG KWONG HON

IPC: H01L21/28 ,  H01L21/335 ,  H01L21/04 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: A method is provided for fabricating a gate structure for a semiconductor device in which the gate structure has an inner spacer. A replacement-gate process is used in which material is removed in a gate region to expose a portion of the substrate; a gate dielectric is formed on the exposed portion of the substrate; and an inner spacer layer is formed overlying the gate dielectric and the dielectric material. A silicon layer is then formed which overlies the inner spacer layer. The structure is then planarized so that portions of the silicon layer and inner spacer layer remain in the gate region. A silicide gate structure is then formed from the silicon; the silicide gate structure is separated from dielectric material surrounding the gate by the inner spacer layer. The semiconductor device may include a first gate region and a second gate region with an interface therebetween, with the inner spacer layer covering the interface. When the device has two gate regions, the process may be used in both gate regions, so as to produce separate silicide structures, with an inner spacer separating the two structures.