公开(公告)号：CA1238124A

公开(公告)日：1988-06-14

申请号：CA499842

申请日：1986-01-17

Applicant: IBM

Inventor： ANDRUSCH GEORG ,  BAISCH JOACHIM ,  BARSUHN HORST ,  WERNICKE FRIEDRICH C ,  WIEDMANN SIEGFRIED K

IPC: G11C29/00 ,  G11C11/401 ,  G11C29/02 ,  G11C29/50 ,  G11C29/56 ,  G01R31/26

Abstract: STABILITY TESTING OF SEMICONDUCTOR MEMORIES Design/test technique to facilitate improved long-term stability testing of static memory arrays with high inherent data retention characteristics at extremely small standby current requirements. The test concept is based on the fact that defects in the standby condition system of a memory array have a bearing on the word line standby potential. Detection of word line potentials differing from their nominal value defined for the standby state, i.e. in the unselected operation mode, is accomplished by performing a disturb write operation into the partly or totally unselected array. As a result cells along a defect word line are less disturbed than those along a good one. This (inverted error pattern) is used for screening defect word lines which otherwise would show up as (long-term) data retention problems.

公开(公告)号：IT8022604D0

公开(公告)日：1980-06-06

申请号：IT2260480

申请日：1980-06-06

Applicant: IBM

Inventor： HEIMEIER HELMUT H ,  KLEIN WIELFRIED ,  KLINK ERICH ,  WERNICKE FRIEDRICH C

IPC: G11C11/41 ,  G11C7/00 ,  G11C11/24 ,  G11C11/40 ,  G11C11/402 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  G11C

Abstract: Semiconductor storage in which the current necessary for reading and/or writing the storage cells is generated simply by discharging input capacitances of the non-selected storage cells and is fed directly to the selected storage cells for reading and/or writing.

公开(公告)号：IT1174672B

公开(公告)日：1987-07-01

申请号：IT2260480

申请日：1980-06-06

Applicant: IBM

Inventor： HEIMEIER HELMUT H ,  KLEIN WIELFRIED ,  KLINK ERICH ,  WERNICKE FRIEDRICH C

IPC: G11C11/41 ,  G11C7/00 ,  G11C11/24 ,  G11C11/40 ,  G11C11/402 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  G11C

Abstract: Semiconductor storage in which the current necessary for reading and/or writing the storage cells is generated simply by discharging input capacitances of the non-selected storage cells and is fed directly to the selected storage cells for reading and/or writing.

公开(公告)号：BR8404041A

公开(公告)日：1985-09-03

申请号：BR8404041

申请日：1984-08-13

Applicant: IBM

Inventor： BROSCH RUDOLF ,  KEINERT JOACHIM ,  KLINK ERICH ,  WERNICKE FRIEDRICH C

IPC: H03K3/286 ,  H03K3/288 ,  H03K5/02 ,  H03K5/151 ,  H03K19/00

Abstract: A phase splitter with latch comprises a true complement generator in the form of a current switch (T1, T2, T3, R3) which supplies two complementary output signals in response to an input signal (VIN). The outputs of this true complement generator are in each case connected to an associated emitter follower (T4, T5). The two emitter followers (T4, T5) have identical emitter resistors (R6, R7) which simultaneously serve as collector load resistors of two cross-coupled transistors (T6, T7) also comprise identical but higher emitter resistors (R13, R14) than the emitter followers (T6, T7). The emitters of the cross-coupled transistors (T6, T7) are each connected to one of the two inputs of an output stage (T8, T9, T11) consisting of a current switch. This current switch is connected to operating voltage (VEE) through a clock-controlled transitor (T11). Upon actuation of the output stage, i.e., when transistor (T11) is on, the active emitter resistance of one of the cross-coupled transistors (T6, T7) is pulled below the value of the emitter resistors (R6, R7) of the emitter followers (T4, T5), thus causing the latch circuit to be latched as a function of the input signal.