公开(公告)号：FR2303381A1

公开(公告)日：1976-10-01

申请号：FR7602995

申请日：1976-01-29

Applicant: IBM ,  IBM

Inventor： BERGER HORST ,  WIEDMANN SIEGFRIED ,  HORST BERGER ET SIEGFRIED WIEDMANN

IPC: H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L29/73 ,  H03K19/091 ,  H01L27/06 ,  H03K19/08

公开(公告)号：FR2319977A1

公开(公告)日：1977-02-25

申请号：FR7619834

申请日：1976-06-24

Applicant: IBM

Inventor： BERGER HORST ,  WIEDMANN SIEGFRIED

IPC: G11C11/41 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/07 ,  H01L27/082 ,  H01L29/08 ,  H01L27/04 ,  G11C11/34

Abstract: The semonconductor structure has at least two components having a common zone. A parasitic thyristor effect can be produced by a minority carrier injection current but is counteracted by means which prevent unwanted coupling between the components. A more highly doped zone is produced in the common zone (2) between transistor base (4) and the zone belonging to a further component. It represents the connection zone for the common zone (2), and forms a barrier (32) for the minority carrier injection current. This arrangement represses coupling interferences, esp. parasitic thyristor effects, while requiring fewer semiconductor surfaces than known solutions.

公开(公告)号：AU4992472A

公开(公告)日：1974-06-13

申请号：AU4992472

申请日：1972-12-11

Applicant: IBM

Inventor： BAITINGER UTZ ,  NAJMANN KNUT ,  REMSHARDT ROLF ,  WIEDMANN SIEGFRIED ,  BERGER HORST ,  PIETRASS HANSJORG

IPC: G11C7/20 ,  G11C11/411 ,  G11C17/08 ,  H01L27/102 ,  H03K3/286 ,  H03K3/356 ,  G11C11/40 ,  H01L19/00

公开(公告)号：FR2335909A1

公开(公告)日：1977-07-15

申请号：FR7634520

申请日：1976-11-08

Applicant: IBM

Inventor： HEUBER KLAUS ,  KLEIN WILFRIED ,  NAJMANN KNUT ,  WIEDMANN SIEGFRIED

IPC: G11C11/41 ,  G11C11/411 ,  G11C11/414 ,  G11C11/415 ,  G11C7/00 ,  G11C11/40

Abstract: An improved method of operating a monolithic memory together with novel and efficient circuitry for practicing said improved method is disclosed. In a bipolar transistor store, or monolithic memory, in accordance with the invention, a very low current (first level) flows from the load elements to the internal cell nodes in the stand-by mode. During the initial portion of a read cycle, current flows from the bit lines to the cell nodes, in addition to the stand-by current (second level). In the recovery period of the read cycle or write cycle a short pulse is added to the stand-by current (third level), thereby reducing the recovery time. The practice of the invention provides a monolithic memory having minimal power requirements and a substantially reduced cycle time.

公开(公告)号：GB1291795A

公开(公告)日：1972-10-04

申请号：GB2859871

申请日：1971-06-18

Applicant: IBM

Inventor： BERGER HORST HEINZ ,  WIEDMANN SIEGFRIED

IPC: G11C11/411 ,  G11C15/00 ,  H01L21/00 ,  H01L27/00 ,  H01L27/07 ,  H01L27/082 ,  H01L27/10 ,  H01L27/102 ,  H03K3/286 ,  H03K3/288 ,  H03K3/35

Abstract: 1291795 Transistor memory cells INTERNATIONAL BUSINESS MACHINES CORP 18 June 1971 [14 July 1970] 28598/71 Addition to 1253763 Heading H3T [Also in Division G4] A bi-stable memory cell Fig. 1 having a pair of load transistors 10, 11 of complementary type to that of a cross-coupled pair T1, T2 as in the parent Specification, has the emitter regions of T1, T2 common with those of a similar cell in the next row, these transistors being formed in this region which acts as a common Z-select line for the two rows. For three dimensional storage, X and Y select lines are also provided, selection being by making X and Z high and Y low. Reading and writing is effected through further transistors T3 T4 whose emitters are connected to bit lines B 1 , B 0 ; these connect to a differential amplifier for reading, and receive different level signals when writing to draw different currents through T10, T11 land thereby differently vary the collector potentials thereof, so setting the bi-stable to a corresponding state. An integrated cell (25, Fig. 3, not shown) has an N region (Z1) forming the emitters of T1, T2, and also forming the same emitters of the adjacent (lower) cell, P diffusions for the bases of T1, T2 and N+ diffusions for their collectors. The base regions of T10, T11 are formed by another N region (Y1) which has a P diffusion connected to X line (X1 ) to form the emitters of T10, T11 of this and the adjacent (upper) cell. L-shaped P diffusions form the collectors of T10, T11 The collectors, bases and emitters of T3, T4 are formed by the N region (Y1), the L-shaped diffusions, and further N+ diffusions therein, respectively.

公开(公告)号：FR2293766A1

公开(公告)日：1976-07-02

申请号：FR7532210

申请日：1975-10-13

Applicant: IBM

Inventor： HEUBER KLAUS ,  KLEIN WILFRIED ,  NAJMANN KNUT ,  WIEDMANN SIEGFRIED

IPC: G11C11/414 ,  G11C11/411 ,  G11C11/415 ,  G11C7/00 ,  G11C11/40